High speed DRAM architecture with uniform access latency
AssigneeMosaid Technologies Incorporated
InventorPaul Demone
Life of this patent
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Abstract
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
Claims18
1-11. (cancelled)
A method for accessing a dynamic random access memory (DRAM), the DRAM having a plurality of memory storage elements located in rows and columns, the method comprising steps of:
- a) initiating a first memory access by providing a first address signal indicative of the location of at least one memory storage element to be accessed;
- b) decoding the first address signal to select a row and at least one column corresponding to the location of the at least one memory storage element;
- c) enabling a word line corresponding to the selected row;
- d) activating a sense amplifier to latch data to or from the at least one selected column;
- e) disabling the word line corresponding to the selected row;
- f) precharging the at least one selected column;
- g) initiating a second memory access by providing a second address signal indicative of the location of at least one memory storage element to be accessed;
- and
- h) decoding the second address signal to select a row and at least one column corresponding to the location of the at least one memory storage element, the second memory access commencing before the step of precharging the selected column has completed.
A dynamic random access memory (DRAM) comprising:
- a) a plurality of memory storage elements located in rows and columns, each memory storage element being coupled to a bit line and a word line;
- b) a row decoder for decoding a row address from an address signal and for asserting a word line signal on a word line corresponding to the decoded row address;
- c) a column decoder for decoding a column address from the address signal and for selecting at least one bit line;
- d) precharge circuitry for precharging the at least one bit line;
- and timing circuitry for controlling the activation of the precharge circuitry such that the precharging occurs at substantially the same time as the address signal is being decoded by the row and column decoders.
Dependencies are inferred from the claim text.