Semiconductor memory storage
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKazuki Tsujimura, Hidenari Kanehara, Norihiko Sumitani
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Abstract
A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.
Claims16
A semiconductor memory storage comprising:
- a memory cell array with a plurality of memory cells arranged in a matrix;
- a plurality of word line drivers connected through word lines to a plurality of the memory cells arranged in a row in said memory cell array for activating said word lines in accordance with the result of decoding an address signal;
- a sense amplifier for detecting the activated state of said memory cells;
- and
- a word line responsive sense amplifier control circuit connected to said word lines for activating said sense amplifier upon activation of said word lines.
A semiconductor memory storage comprising:
- a memory cell array with a plurality of memory cells arranged in a matrix;
- a plurality of word line drivers each connected through a word line to a plurality of memory cells arranged in a row in said memory cell array for activating said word line in accordance with the result of decoding an address signal;
- and
- a sense amplifier connected to a pair of bit lines connected to a plurality of the memory cells in a column for detecting the potential difference generated between said bit lines by the operation of reading said memory cells;
- said semiconductor memory storage further comprising:
- a plurality of n-channel field-effect transistors each with the gate thereof connected to the corresponding one of said word lines and the drain thereof connected to the high potential side of a power supply;
- a plurality of replica n-channel field-effect transistors inserted in parallel between a dummy bit line and the grounding potential, the gate of each of said replica n-channel field-effect transistors being connected to the source of the corresponding one of said n-channel field-effect transistors;
- and
- a logic gate for outputting a read enable signal as an enable signal for said sense amplifier in response to the discharge of said dummy bit line in response to the turning on of said replica n-channel field-effect transistors.
Dependencies are inferred from the claim text.