Vertical NROM having a storage density of 1 bit per 1F2

A method for forming a memory array, comprising:

• forming two raised areas on a substrate, defining a trench therebetween;
• forming two vertical multiple bit cells on the sidewalls of the trench,
• wherein forming the each vertical multiple bit cell includes,
• forming a vertical transistor extending outwardly from a selected sidewall, the transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the first and second source/drain regions of the transistor share the first and second source/drain regions of a second transistor respectively;
• forming a first transmission line coupled to the first source/drain region, and
• forming a second transmission line coupled to the second source/drain region;
• forming at least one word line, where the at least one word line is formed parallel to the trench and is coupled to the gates of one or more multiple bit cell transistors on each sidewall of the trench;
• and
• wherein forming the transistor includes forming a transistor adapted to have a charge programmed in either a first storage region or a second storage region in the gate insulator and to be operated with either the first source/drain region or the second source/drain region serving as the source region such that the programmed transistor operates at reduced drain source current.

A vertical multiple bit cell structure, comprising:

• two raised areas on a substrate, defining a trench therebetween;
• a first vertical multiple bit cell formed on a first sidewall of the trench and a second vertical multiple bit cell formed on a second sidewall of the trench, wherein the first and second vertical multiple bit cell includes,
• a vertical transistor extending outwardly from a selected sidewall, the transistor having, a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator;
• and
• wherein at least one of the multiple bit cells is adapted to have a charge programmed in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the first source/drain region a second voltage threshold region (Vt2) adjacent to the second source/drain region which vary depending on in which direction the transistor is operated.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, the memory device having a memory array, the memory array comprising:
• a number of vertical transistors extending outwardly from a substrate and separated by trenches, wherein each transistor includes a first source/drain region, a second source/drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator;
• a number of first transmission lines coupled to the first source/drain region of each vertical transistor along columns of the memory array;
• a number of wordlines formed along rows of the memory array and coupled to the gate of each vertical transistor;
• and
• a number of second transmission lines coupled to the second source/drain region of each vertical transistor along columns of the memory array;
• wherein at least one of the transistors is adapted to have a charge programmed in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the first source/drain region a second voltage threshold region (Vt2) adjacent to the second source/drain region which vary depending on in which direction the transistor is operated;
• and
• wherein the first and second source/drain regions of the transistor share both the first and second source/drain regions respectively from another of the vertical multiple bit cells.

A memory device, comprising:

• a memory array, the memory array comprising:
• a number of vertical transistors extending outwardly from a substrate and separated by trenches, wherein each transistor includes a first source/drain region, a second source/drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator;
• a number of first transmission lines coupled to the first source/drain region of each vertical transistor along columns of the memory array;
• a number of wordlines formed along rows of the memory array and coupled to the gate of each vertical transistor;
• and
• a number of second transmission lines coupled to the second source/drain region of each vertical transistor along columns of the memory array;
• wherein at least one of transistors is adapted to have a charge programmed in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region such that the channel region has a first voltage threshold region (Vt I) adjacent to the first source/drain region a second voltage threshold region (Vt2) adjacent to the second source/drain region which vary depending on in which direction the transistor is operated;
• and
• wherein the first and second source/drain regions of the transistor share both the first and second source/drain regions respectively from another of the vertical multiple bit cells.