Flash memory data bus for syncronous burst read page

A method of operating a memory device comprising:

• receiving an address, having a row address, a column address, and an initial data word offset address;
• selecting a column page with the address from a memory array having a plurality of memory cells;
• dividing the column page into a plurality of data word sets based on the offset address, wherein each data word set contains an equal number of one or more data words;
• selecting and sensing an initial data word set of the column page, wherein the initial data word set begins with the data word of the data word offset address;
• selecting and sensing a following sequential data word set of the column page while reading the individual data words of the initial data word set sequentially from the memory device;
• and
• selecting and sensing any further following sequential data word sets of the column page while reading the individual data words of a previously sensed data word set sequentially from the memory device until all the data word sets of the selected column page have been read.

A method of operating a Flash memory device comprising:

• receiving an address, having a row address, a column address, and an initial data word offset address;
• selecting a column page with the address from a memory array having a plurality of floating gate memory cells;
• dividing the column page into two data word sets based on the offset address, wherein each data word set contains an equal number of two or more data words;
• selecting and sensing a first data word set of the column page, wherein the first data word set contains the initial data word offset address;
• latching the first data word set in to an intermediate column latch, wherein the intermediate latch circuit contains a plurality of latch groups, each latch group having a plurality of latch circuits and latches a single data word;
• selecting and sensing a second sequential data word set of the column page while reading the individual data words of the first data word set sequentially from the Flash memory device;
• and
• latching the second data word set in the intermediate latch circuit after all but a final data word of the first data word set has been read from the Flash memory device, such that all latch groups of the intermediate latch circuit except for a first group of latches that is currently selected and contains the final selected data word are clocked;
• and
• latching a final data word of the second data word set in the intermediate latch circuit after the final data word of the first data word set has been read from the Flash memory device, such that all latch groups of the intermediate latch circuit except for a second group of latches that is currently selected and contains a first selected data word of the second data word set are clocked to complete latching the second data set.

A method of operating a latch circuit comprising:

• latching a first set of data words;
• latching a first portion of a second set of data words while reading a last word of the first set of data words;
• and
• latching a second portion of the second set of data words after reading the last word of the first set of data words.

A method of operating intermediate data word latches, comprising:

• latching a first data word set, wherein the intermediate latch circuit contains a plurality of latch groups, each latch group having a plurality of latch circuits and latches a data word;
• latching a second data word set in the intermediate latch circuit after all but a final data word of the first data word set has been sequentially read, such that all latch groups of the intermediate latch circuit except for a first group of latches that is currently selected and contains the final selected data word are clocked;
• and
• latching only the first group of latches after the final selected data word of the first data word set is sequentially read to complete latching the second data set.

A method of operating intermediate data word latches, comprising:

• latching a first data word set, wherein the intermediate latch circuit contains a plurality of latch groups, each latch group having a plurality of latch circuits and latch a single data word;
• latching a second data word set in the intermediate latch circuit after all but a final data word of the first data word set has been sequentially read from the intermediate latch circuit, such that all latch groups of the intermediate latch circuit except for a first group of latches that is currently selected and contains the final selected data word are clocked;
• and
• latching a final data word of the second data word set in the intermediate latch circuit after the final data word of the first data word set has been read from the intermediate data latch circuit, such that all latch groups of the intermediate latch circuit except for a second group of latches that is currently selected and contains a first selected data word of the second data word set are clocked to complete latching the second data set.

A memory device comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• an address circuit, adapted to receive a memory address;
• a row decoder coupled to the address latch circuit and the memory array, wherein the row decoder is adapted to access a selected row page of memory from the memory array;
• a column decoder coupled to the address latch circuit and the memory array, wherein the column decoder is adapted to access a selected column page having a number of bitlines from the memory array;
• a decoder circuit coupled to the address circuit, wherein the decoder circuit is adapted to select a set of data words from the selected column page, each data word having a plurality of bitlines;
• a multiplexer coupled to the decoder circuit;
• a plurality of sense amplifiers, wherein the multiplexer is adapted to selectively couple the plurality of bitlines of each data word of the selected set of data words to the plurality of sense amplifiers, and wherein the number of bitlines of the selected column page is greater than the number of the plurality of sense amplifiers;
• an intermediate latch circuit having a plurality of data word latch groups coupled to the sense amplifiers;
• an intermediate latch control circuit coupled to the intermediate latch control circuit, wherein the intermediate latch control circuit is adapted to clock the intermediate latches to latch in a first set of data words;
• and
• wherein the intermediate latch circuit is adapted to latch in a new data word set while a final data word is read from a current data word set held in the intermediate data latch circuit in a multiple trigger latching action, such that there are no gaps in reading the final data word of the current data word set and a first data word of the new data word set.

A Flash memory device comprising:

• a memory array having a plurality of floating gate memory cells arranged in rows and columns;
• an address circuit, adapted to receive a memory address;
• a row decoder coupled to the address latch circuit and the memory array, wherein the row decoder is adapted to access a selected row page of memory from the memory array;
• a column decoder coupled to the address latch circuit and the memory array, wherein the column decoder is adapted to access a selected column page having a number of bitlines from the memory array;
• a decoder circuit coupled to the address circuit, wherein the decoder circuit is adapted to select a set of data words from the selected column page, each data word having a plurality of bitlines;
• a multiplexer coupled to the decoder circuit;
• a plurality of sense amplifiers, wherein the multiplexer is adapted to selectively couple the plurality of bitlines of each data word of the selected set of data words to the plurality of sense amplifiers, and wherein the number of bitlines of the selected column page is greater than the number of the plurality of sense amplifiers;
• an intermediate latch circuit having a plurality of data word latch groups coupled to the sense amplifiers;
• wherein the intermediate latch circuit is adapted to latch in a first set of data words;
• wherein the decoder circuit is adapted to select and couple a second set of data words to the plurality of sense amplifiers after the first set of data words have been latched into the intermediate latches;
• and
• wherein the intermediate latch circuit is adapted to latch the second set of sensed data words into the intermediate latch circuit upon the selection of a final data word of the first set of data words, such that all latches of the intermediate latch circuit except for a first group of latches upon the selection of a final data word of the first set of data words are clocked, and all latches of the intermediate latch circuit except for a second group of latches when a first data word of the second data set is selected.

A Flash memory device comprising:

• a memory array having a plurality of floating gate memory cells arranged in rows and columns;
• an address circuit, adapted to receive and latch the memory address upon receiving an address valid signal on an address valid input;
• a clock signal input adapted to receive a clock signal;
• a row decoder coupled to the address latch circuit and the memory array, wherein the row decoder is adapted to access a selected row page of memory from the memory array;
• a column decoder coupled to the address latch circuit and the memory array, wherein the column decoder is adapted to access a selected column page having a number of bitlines from the memory array;
• a decoder circuit coupled to the address circuit, wherein the decoder circuit is adapted to select a first and second set of data words from a starting address offset from the selected column page, each data word having a plurality of bitlines;
• a multiplexer coupled to the decoder circuit;
• a plurality of sense amplifiers, wherein the multiplexer is adapted to selectively couple the plurality of bitlines of each data word of a selected set of data words to the plurality of sense amplifiers, and wherein the number of bitlines of the selected column page is greater than the number of the plurality of sense amplifiers;
• a latency counter, wherein the latency counter is adapted to output a latency timeout signal when a minimum latency time for the sense amplifiers to sense a set of data words expires;
• a sense amplifier enable circuit coupled to the address valid input and the latency counter, wherein the sense amplifier enable circuit is adapted to produce a sense amplifier enable signal of a selected duration upon receiving an address valid signal or a latency timeout signal;
• an intermediate latch circuit having a plurality of data word latch groups coupled to the sense amplifiers;
• an intermediate latch control circuit coupled to the intermediate latch control circuit, wherein the intermediate latch control circuit is adapted to clock the intermediate latches to latch in a first set of data words from the sense amplifiers when the sense amplifier enable signal expires;
• an address counter coupled to the intermediate latch control circuit, wherein the address counter is adapted to load the starting address offset from the address latch and increment on each clock signal pulse after expiration of the latency counter;
• a data input/output;
• a data word decoder coupled to the address counter, wherein the data word decoder is adapted to couple a selected data word latch group from the intermediate latches to the data input/output according to the address value of the address counter;
• wherein the decoder circuit is adapted to select and couple a second set of data words to the plurality of sense amplifiers after expiration of the latency counter and the first set of data words have been sensed and latched into the intermediate latches;
• and
• wherein the intermediate latch circuit is adapted to latch the second set of sensed data words upon the selection of a final data word of the first set of data words by the data word decoder, such that the intermediate latch control circuit is adapted to clock all latches of the intermediate latch circuit except for a first group of latches containing the final data word of the first data word set and the intermediate latch control circuit is adapted to clock all latches of the intermediate latch circuit except for a second group of latches containing a first data word of the second data set, when the first data word is selected by the data word decoder.

A decoder circuit, comprising:

• an address input having a control address and an offset address;
• a plurality of cells having a carry input and a carry output, wherein each cell is adapted to activate with a selected offset address and to decode a selected group of data words utilizing a coupled control address, where the carry input of each cell is coupled the carry output of a lower addressed previous cell of the plurality of cells, and where each data word in the group of data words is from a separate data word set of a plurality of data word sets of a column page;
• wherein the carry input of a first cell is coupled to a first logic state;
• wherein each cell is adapted to decode an input control address and select a data word of its assigned group of data words from a first data word set upon receiving a first logic state on its carry input;
• wherein each cell is adapted to decode an input control address and select a data word of its assigned group of data words from a second data word set upon receiving a second logic state on its carry input;
• and
• wherein each cell is adapted to select a data word of its assigned group of data words from a second data word set and invert the state of the input carry from logical first state to logical second state on its carry output upon matching its assigned input offset address.

A latch circuit, comprising:

• a plurality of latch groups, each latch group having a plurality of latches and stores a single data word;
• wherein the latch circuit is adapted to latch a first set of data words into the plurality of latch groups of the latch circuit;
• and
• wherein the latch circuit is adapted to latch a second set of data words while a first selected latch group containing a data word of the first set of data words and second selected latch group containing a data word of the second set of data words are sequentially accessed, such that all latch groups of the latch circuit except for the first selected latch group are clocked while the first selected latch group are accessed, and all latch groups of the latch circuit except for the second selected latch group are clocked while the second selected latch group are accessed.

An intermediate latch circuit, comprising:

• a plurality of latch groups, each latch group having a plurality of latch circuits and adapted to store a single data word;
• wherein the intermediate latch circuit is adapted to latch a first set of data words into the plurality of latch groups;
• and
• wherein the intermediate latch circuit is adapted to latch a second set of data words while a first latch group containing a final data word of the first set of data words and a second latch group containing a first data word of the second set of data words are sequentially accessed, such that all latch groups of the intermediate latch circuit except for the first latch group are clocked while the first latch group is accessed, and only the first latch group is clocked while the second latch group is accessed.

A system, comprising:

• a host coupled to a memory device, wherein the memory device comprises,
• a memory array having a plurality of floating gate memory cells arranged in rows and columns;
• an address circuit, adapted to receive a memory address;
• a row decoder coupled to the address latch circuit and the memory array, wherein the row decoder is adapted to access a selected row page of memory from the memory array;
• a column decoder coupled to the address latch circuit and the memory array, wherein the column decoder is adapted to access a selected column page having a number of bitlines from the memory array;
• a decoder circuit coupled to the address circuit, wherein the decoder circuit is adapted to select a set of data words from the selected column page, each data word having a plurality of bitlines;
• a multiplexer coupled to the decoder circuit;
• a plurality of sense amplifiers, wherein the multiplexer is adapted to selectively couple the plurality of bitlines of each data word of the selected set of data words to the plurality of sense amplifiers, and wherein the number of bitlines of the selected column page is greater than the number of the plurality of sense amplifiers;
• an intermediate latch circuit having a plurality of data word latch groups coupled to the sense amplifiers;
• wherein the intermediate latch circuit is adapted to latch in a first set of data words;
• wherein the decoder circuit is adapted to select and couple a second set of data words to the plurality of sense amplifiers after the first set of data words have been latched into the intermediate latches;
• and
• wherein the intermediate latch circuit is adapted to latch the second set of sensed data words into the intermediate latch circuit upon the selection of a final data word of the first set of data words, such that all latches of the intermediate latch circuit except for a first group of latches upon the selection of a final data word of the first set of data words are clocked, and all latches of the intermediate latch circuit except for a second group of latches when a first data word of the second data set is selected.