US 2004/0202026 A1Published application

High speed latch and compare function

AssigneeInternational Business Machines Corporation

InventorsPaul A. Bunce, John D. Davis, Donald W. Plass

Life of this patent

Estimating the term…

Abstract

A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

Claims12

Dependent claims

A latch and compare apparatus for reading and comparing a RAM, said latch and compare apparatus comprising a dual rail output from the RAM and at least two latches associated with the dual rail output, at least one latch indicating if a “0” was read from the RAM and at least one latch indicating a “1” was read from the RAM.

Dependencies are inferred from the claim text.

Facts

Application: 10/413,615Filed 14 Apr 2003
Published: 14 Oct 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0895
Caches characterised by their organisation or structure: of parts of caches, e.g. directory or tag array
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 15/04
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out…
G11C 2207/104
Aspects relating to interfaces of memory device to external buses: embedded memory devices, e.g. memories with a processing device on the same die…

Family

US 6,822,885 B2Related patent
US 2004/0202026 A1This patent

From the US filing history. Foreign family members aren’t listed.

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