# US 2004/0202022 A1 · Shared volatile and non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2004/0202022 A1 - Document ID: US20040202022A1 - Status: Published application - Kind: A1 - Application number: 10/697,367 - Filed: 2003-10-30 - Published: 2004-10-14 - Earliest claimed: 2002-07-15 - Assignees: Hewlett-Packard Development Company, L.P. - Inventors: Manish Sharma; Frederick Perner - Web page: https://patentgrep.com/patent/US20040202022A1 ## CPC - G11C 14/0036: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell} - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell - G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell - G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells. ## Claims ### Claim 1 A memory back-up system comprising: a first memory cell; a non-volatile memory cell that is interfaced to the first memory cell; control circuitry that allows data to be written to one of the first memory cell and the non-volatile memory cell, and that provides transfer of the data from one of the first memory cell and the non-volatile memory cell to the other one of the first memory cell and the non-volatile memory cell. ### Claim 2 (depends on 1) The memory back-up system of claim 1, wherein the control circuitry further includes allowing data to be read from one of the first memory cell and the non-volatile memory cell. ### Claim 3 (depends on 1) The memory back-up system of claim 1, wherein the first memory cell and the non-volatile memory cell are integrated on a common substrate. ### Claim 4 (depends on 1) The memory back-up system of claim 1, wherein the non-volatile memory cell is an MRAM memory cell. ### Claim 5 (depends on 1) The memory back-up system of claim 1, wherein the non-volatile memory cell comprises at least one of MRAM memory, ferro-electric FeRAM, and Flash memory. ### Claim 6 (depends on 1) The memory back-up system of claim 1, wherein the first memory cell is formed adjacent to a substrate, and the non-volatile memory cell is formed adjacent to the first memory cell. ### Claim 7 (depends on 1) The memory back-up system of claim 1, further comprising a plurality of first memory cells and a plurality of non-volatile memory cells. ### Claim 8 (depends on 7) The memory back-up system of claim 7, wherein the plurality of first memory cells and the plurality of non-volatile memory cells are integrated on a common substrate. ### Claim 9 (depends on 7) The memory back-up system of claim 7, wherein the plurality of first memory cells and the plurality of non-volatile memory cells are accessed through a common set of access control lines. ### Claim 10 (depends on 9) The memory back-up system of claim 9, wherein the common set of access control lines comprise at least one of row select lines and column select lines. ### Claim 11 (depends on 7) The memory back-up system of claim 7, wherein the plurality of first memory cells and the plurality of non-volatile memory cells comprise a shared set of wide data lines. ### Claim 12 (depends on 11) The memory back-up system of claim 11, wherein the shared set of wide data lines comprises at least 256 data lines. ### Claim 13 A memory back-up system comprising: a volatile memory cell; a non-volatile memory cell that is interfaced with the volatile memory cell; a common control line connected to the volatile memory cell and the non-volatile memory cell, the common control line allowing data to be simultaneously written to the volatile memory cell and the non-volatile memory cell. ### Claim 14 (depends on 13) The memory back-up system of claim 13, wherein the volatile memory cell is a DRAM memory cell and the non-volatile memory cell is an MRAM memory cell. ### Claim 15 (depends on 13) The memory back-up system of claim 13, further comprising a second control line which in combination with the common control line provides selection of the volatile memory cell. ### Claim 16 (depends on 13) The memory back-up system of claim 13, further comprising a third control line which in combination with the common control line provides selection of the non-volatile memory cell. ### Claim 17 (depends on 13) The memory back-up system of claim 13, further comprising a an array volatile memory cells; an array of non-volatile memory cells, each non-volatile memory cell interfaced with a corresponding volatile memory cell; a plurality of common control lines, each common control line connected to a corresponding plurality of volatile memory cells and the non-volatile memory cells, the common control line allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells. ### Claim 18 A memory back-up system comprising: a plurality of first memory cells; a plurality of non-volatile memory cells that are interfaced to the first memory cells; control circuitry that allows data to be written to one of the first memory cells and the non-volatile memory cells, and that provides transfer of the data from one of the first memory cells and the non-volatile memory cells to the other one of the first memory cells and the non-volatile memory cells. ### Claim 19 (depends on 18) The memory back-up system of claim 18, wherein the control circuitry further includes allowing data to be read from one of the first memory cell and the non-volatile memory cell. ### Claim 20 A computing device comprising: a controller; a memory unit interfaced with the controller, the memory unit comprising; an array volatile memory cells; an array of non-volatile memory cells, each non-volatile memory cell interfaced with a corresponding volatile memory cell; and a plurality of common control lines, each common control line connected to a corresponding plurality of volatile memory cells and the non-volatile memory cells, the common control line allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells. ### Claim 21 An image storing device comprising: means for receiving an image; a memory unit for storing the image, the memory unit comprising; an array volatile memory cells; an array of non-volatile memory cells, each non-volatile memory cell interfaced with a corresponding volatile memory cell; and a plurality of common control lines, each common control line connected to a corresponding plurality of volatile memory cells and the non-volatile memory cells, the common control line allowing data to be simultaneously written to the corresponding plurality of volatile memory cells and the non-volatile memory cells.