Semiconductor device
AssigneeRenesas Technology Corp.
InventorsMasamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
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AssigneeRenesas Technology Corp.
InventorsMasamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
Estimating the term…
The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.
A semiconductor integrated circuit comprising a nonvolatile memory enabling electric erase and write over a semiconductor substrate,
A semiconductor integrated circuit comprising:
A semiconductor integrated circuit comprising a nonvolatile memory enabling electric erase and write on a semiconductor substrate,
21-25. (canceled).
Dependencies are inferred from the claim text.