Low-current and high-speed phase-change memory devices and methods of driving the same
AssigneeSamsung Electronics Co., Ltd.
InventorSe-ho Lee
Life of this patent
Estimating the term…
Abstract
Phase-change memories in which phase is changed by varying the resistance by a small amount are provided. In the phase-change memory, a set state is defined as a state where amorphous nuclei are formed in a phase-change layer of a memory cell and the phase-change layer has an initial resistance that is higher than in a crystalline matrix, and a reset state is defined as a state where the number and/or the density of the amorphous nuclei are greater than those in the set state and a resistance is higher than in the set state. A current for writing the reset and set states is reduced to several hundred microamperes, and a period required for writing the reset and set states is reduced to several tens of nanoseconds to several hundred nanoseconds.
Claims41
A method of establishing a state of a phase-change memory, comprising:
- writing a reset state as a high-resistance state by applying a reset current of about ten microamperes to several hundred microamperes to a phase-change layer of a phase-change memory cell for a period of from about 10 nanoseconds to about 100 nanoseconds;
- and
- writing a set state as a low-resistance state by applying a set current of less than about several tens of microamperes to the phase-change layer for a period of from about 10 nanoseconds to about 100 nanoseconds.
A method of driving a phase-change memory, the method comprising:
- writing a set state by applying a set current of from about 30 μA to about 50 μA to a crystalline phase-change layer of a memory cell;
- and
- writing a reset state by applying a reset current of from about 60 μA to about 200 μA to the phase-change layer, wherein the reset state is defined as a state where a resistance of the phase-change layer is greater than in the set.
A phase-change memory comprising:
- a first electrode contact;
- a phase-change layer on the first electrode contact;
- and
- a second electrode contact on the phase-change layer,
- wherein a set state is a state in which amorphous nuclei are formed in the phase-change layer that has a set resistance of from about 4 kΩ to 6 kΩ, and a reset state is a state in which the number and density of the amorphous nuclei are greater than in the set state and has a reset resistance of about 6 kΩ to 20 kΩ.
A phase-changeable memory device, comprising:
- a phase change memory cell;
- and
- a sense amplifier circuit configured to detect a change in resistance of the phase change memory cell from a first resistance associated with a first state of the phase change memory cell to a second resistance associate with a second state of the phase change memory cell, the second resistance being from about 1.5 to about 3 times the first resistance.
A phase change memory, comprising:
- first and second electrode contacts;
- a phase-change layer between the first and second electrode contacts, the phase change layer providing a first state established by a first number of amorphous nuclei in a crystalline matrix in a region adjacent an interface between the phase-change layer and the first electrode.
A method of operating a phase change memory, comprising:
- establishing logic states in a phase change memory by controlling amorphous nucleation in a crystalline matrix of a phase-changeable material.
Dependencies are inferred from the claim text.