Differential negative resistance memory
AssigneeMicron Technology, Inc.
InventorKristy A. Campbell
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Abstract
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes and to methods of making such a device. The stored data is semi-volatile. Generally, information written to a device in accordance with the invention can maintain its memory for a matter of minutes, hours, or days before a refresh is necessary. The power requirements of the device are far reduced compared to DRAM. The memory function of the device is highly stable, repeatable, and predictable. The device can be produced in a variety of ways.
Claims95
A differential negative resistance memory device, comprising:
- a first electrode and a second electrode;
- and
- a resistance variable region separating said first and second electrodes and in electrical communication therewith, said resistance variable region exhibiting differential negative resistance memory behavior and storing at least one memory state as a read current amplitude in response to applied voltage.
A memory device, comprising:
- an anode;
- a chalcogenide-based region over said anode, said region having at least two programmable and maintainable differential negative resistance read current states;
- a cathode over said chalcogenide-based region;
- and
- a sensing device in electrical communication with said chalcogenide-based region, said sensing device being able to sense said at least two read current states as at least two read current states in response to an applied read voltage.
A differential negative resistance memory device, comprising:
- a substrate;
- a first conductive layer over said substrate;
- a first germanium selenide layer over said first conductive layer;
- a silver selenide layer over said first germanium selenide layer;
- a second germanium selenide layer over said silver selenide layer, wherein said first and second germanium selenide layers have a chemical formula GexSe100-x, x being in the range of about 18-43;
- a silver layer over said second germanium selenide layer;
- and
- a second conductive layer over said silver layer;
- wherein said device has a differential negative resistance memory such that it is programmable to a higher current flow read state and a lower current flow read state in response to applied first and second programming voltages, respectively.
A processor system, comprising;
- a processor;
- a differential negative resistance memory device, said memory device comprising;
- a first electrode and a second electrode;
- and
- a resistance variable region separating said first and second electrodes and in electrical communication therewith, said resistance variable region exhibiting differential negative resistance memory behavior as storing at least one memory state as a read current in response to an applied voltage.
A method of forming a differential negative resistance memory device, comprising:
- forming a first electrode;
- forming a resistance variable region over said first electrode;
- forming a second electrode over said resistance variable region;
- and
- inducing differential negative resistance memory behavior in said resistance variable region.
A method of forming a memory device, comprising:
- providing a substrate;
- forming a first electrode layer over said substrate;
- forming a first GexSe100-x layer over said first electrode layer;
- forming a Ag2Se layer over said GexSe100-x layer;
- forming a second GexSe100-x layer over said Ag2Se layer;
- forming a second electrode layer over said second GexSe100-x layer;
- forming a pattern over said second electrode layer and etching to said first electrode layer;
- and
- inducing repeatable and maintainable differential negative resistance behavior in said memory device.
A method of forming a memory device, comprising
- providing a substrate;
- forming a first electrode layer over said substrate;
- forming a dielectric layer over said first electrode layer;
- forming a via in said dielectric layer to expose a portion of said first electrode layer;
- forming a GexSe100-x within said via and over said first electrode layer;
- forming a Ag2Se layer within said via and over said GexSe100-x layer;
- forming a second GexSe100-x layer over said Ag2Se layer;
- forming a second electrode layer over said second GexSe100-x layer;
- planarizing to said dielectric layer;
- forming an insulating layer over said second electrode layer and said dielectric layer;
- and
- inducing repeatable and semi-volatile differential negative resistance memory behavior in said memory device.
Dependencies are inferred from the claim text.