Back to results
US 2004/0201789 A1Published application
Active matrix substrate and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorMasahiko Akiyama
Life of this patent
Estimating the term…
Abstract
A method of manufacturing an active matrix substrate comprises forming a plurality of elements on an element formation substrate, forming wirings on a final substrate, transferring some elements selected from the elements, and selectively connecting some elements to the wirings on the final substrate. According to this method, it is possible to manufacture an active matrix substrate providing a high definition image on a large substrate or a non-glass substrate, at a low cost.
Claims20
An active matrix substrate comprising:
- a substrate;
- a first wiring formed on said substrate;
- an interlayer insulating layer formed over said substrate having said first wiring formed thereon;
- a second wiring formed on said interlayer insulating layer;
- a driving circuit including at least one active element formed above said interlayer insulating layer with an adhesion layer interposed therebetween, said at least one active element comprising a semiconductor layer, a source electrode and a drain electrode both connected to said semiconductor layer, and a gate electrode formed on said semiconductor layer with a gate insulating layer interposed therebetween;
- one of said first wiring and said second wiring connected to said gate electrode of said at least one active element by a first connecting electrode;
- the other of said first wiring and said second wiring connected to said source electrode of said at least one active element by a second connecting electrode;
- and
- a pixel electrode connected to said drain electrode of said at least one active element.
6 more elements
An active matrix substrate comprising:
- a substrate;
- a first wiring formed on said substrate;
- a driving circuit including at least one active element formed above said substrate with an adhesion layer interposed therebetween, said at least one active element comprising a semiconductor layer, a source electrode and a drain electrode both connected to said semiconductor layer, and a gate electrode formed on said semiconductor layer with a gate insulating layer interposed therebetween;
- an interlayer insulating layer formed over said substrate having said first wiring formed thereon;
- a second wiring formed above said interlayer insulating layer;
- one of said first wiring and said second wiring connected to said gate electrode of said at least one active element by a first connecting electrode;
- the other of said first wiring and said second wiring connected to said source electrode of said at least one active element by a second connecting electrode;
- and
- a pixel electrode formed above said interlayer insulating layer and connected to said drain electrode of said at least one active element via a third connecting electrode.
6 more elements
Dependencies are inferred from the claim text.