Phase locked loop that avoids false locking

A phase locked loop (PLL) comprises:

• difference detector operably coupled to determine a difference signal between a feedback oscillation and a reference oscillation;
• loop filter operably coupled to produce a control signal from the difference signal;
• controlled oscillation module operably coupled to produce an output oscillation based on the control signal;
• frequency translation module;
• and
• divider module operably coupled in series with the frequency translation module, wherein the series combination of the divider module and the frequency translation module is operably coupled to produce an intermediate feedback oscillation from the output oscillation and to produce the feedback oscillation from the intermediate feedback oscillation, wherein the intermediate feedback oscillation is of a frequency, with respect to the reference oscillation and the output oscillation, to substantially avoid false locking of the PLL.

A phase shift keying (PSK) modulator comprises:

• difference detector operably coupled to determine a difference signal between a feedback oscillation and a reference oscillation;
• loop filter operably coupled to produce a control signal from the difference signal;
• controlled oscillation module operably coupled to produce, in accordance with an adjustable operating parameter of the controlled oscillation module, a modulated output oscillation based on the control signal, wherein the adjustable operating parameter is set based on desired operating conditions of the PSK modulator such that false locking of the PSK modulator is substantially avoided;
• frequency translation module operably coupled to produce a translation oscillation from the modulated output oscillation based on a frequency translation rate;
• and
• modulation mixing module operably coupled to mix data with the translation oscillation to produce the feedback oscillation.

A phase shift keying (PSK) modulator comprises:

• difference detector operably coupled to determine a difference signal between a feedback oscillation and a reference oscillation;
• loop filter operably coupled to produce a control signal from the difference signal;
• controlled oscillation module operably coupled to produce a modulated output oscillation based on the control signal;
• frequency translation module;
• divider module operably coupled in series with the frequency translation module, wherein the series combination of the divider module and the frequency translation module is operably coupled to produce an intermediate feedback oscillation from the modulated output oscillation and to produce a translation oscillation from the intermediate feedback oscillation, wherein the intermediate feedback oscillation is of a frequency, with respect to the reference oscillation and the modulated output oscillation, to substantially avoid false locking of the PLL;
• and
• modulation mixing module operably coupled to mix data with the translation oscillation to produce the feedback oscillation.

A radio frequency integrated circuit (RFIC) comprises:

• transmitter section operably coupled to convert outbound data into outbound radio frequency (RF) signals based on a transmitter local oscillation;
• receiver section operably coupled to convert inbound RF signals into inbound data based on a receiver local oscillation;
• and
• local oscillator operably coupled to produce the transmitter local oscillation and the receiver local oscillation, wherein the local oscillator includes:
• difference detector operably coupled to determine a difference signal between a feedback oscillation and a reference oscillation;
• loop filter operably coupled to produce a control signal from the difference signal;
• controlled oscillation module operably coupled to produce, in accordance with an adjustable operating parameter of the controlled oscillation module, an output oscillation based on the control signal, wherein the adjustable operating parameter is set based on desired operating conditions of the PLL such that false locking of the PLL is substantially avoided;
• and
• frequency translation module operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

A radio frequency integrated circuit (RFIC) comprises:

• transmitter section operably coupled to convert outbound data into outbound radio frequency (RF) signals based on a transmitter local oscillation;
• receiver section operably coupled to convert inbound RF signals into inbound data based on a receiver local oscillation;
• and
• local oscillator operably coupled to produce the transmitter local oscillation and the receiver local oscillation, wherein the local oscillator includes:
• difference detector operably coupled to determine a difference signal between a feedback oscillation and a reference oscillation;
• loop filter operably coupled to produce a control signal from the difference signal;
• controlled oscillation module operably coupled to produce an output oscillation based on the control signal;
• frequency translation module;
• and
• divider module operably coupled in series with the frequency translation module, wherein the series combination of the divider module and the frequency
• translation module is operably coupled to produce an intermediate feedback oscillation from the output oscillation and to produce the feedback oscillation from the intermediate feedback oscillation, wherein the intermediate feedback oscillation is of a frequency, with respect to the reference oscillation and the output oscillation, to substantially avoid false locking of the PLL.