Back to results
US 2004/0201410 A1Published application
Level shifter
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsJun Koyama, Munehiro Azami, Yutaka Shionoiri, Tomoaki Atsumi
Life of this patent
Estimating the term…
Abstract
A level shifter that accommodates lower driving voltage of a driver circuit and has a sufficient capability of converting the amplitude of an input signal even when the voltage amplitude of the input signal is low is provided. A level shifter utilizing a current mirror circuit 150 and a differential circuit 160 is used in a portion for converting the voltage amplitude of the signal. Since the potential difference of a signal input through transistors 105 and 106 to the differential circuit 120 is amplified and outputted, the voltage amplitude can be normally converted without influence of the threshold of a transistor even when the voltage amplitude of the input signal is low.
Claims46
1-54 (Canceled)
A semiconductor device having a level shifter, the level shifter comprising:
- a current mirror circuit;
- a differential circuit having the current mirror circuit as a load;
- a current source for supplying current to the differential circuit;
- and
- first and second source follower circuits,
- wherein a first input signal is input to the first source follower circuit,
- wherein a first output signal from the first source follower circuit is input to the differential circuit,
- wherein a second input signal is input to the second source follower circuit, and
- wherein a second output signal from the second source follower circuit is input to the differential circuit.
6 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a current mirror circuit;
- a differential circuit having the current mirror circuit as a load;
- a first current source for supplying current to the differential circuit;
- a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
- a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
- and
- second and third current sources for supplying current to the first and second transistors, respectively,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal from the first transistor is input to the differential circuit,
- wherein a second input signal is input to a second source region of the second transistor, and
- wherein a second output signal from the second transistor is input to the differential circuit.
8 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a current mirror circuit;
- a differential circuit having the current mirror circuit as a load;
- a first current source for supplying current to the differential circuit;
- a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
- a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
- and
- second and third current sources for supplying current to the first and second transistors, respectively,
- wherein the differential circuit comprises third and fourth transistors,
- wherein the first drain region of the first transistor and a third gate electrode of the third transistor are electrically connected to each other,
- wherein the second drain region of the second transistor and a fourth gate electrode of the fourth transistor are electrically connected to each other,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal is input to a third gate electrode of the third transistor,
- wherein a second input signal is input to a second source region of the second transistor, and
- wherein a second output signal is input to a fourth gate electrode of the fourth transistor.
11 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a first transistor of a first conductive type, having a first gate electrode and a first drain region thereof being electrically connected to each other;
- a second transistor of the first conductive type, having a second gate electrode and a second drain region thereof being electrically connected to each other;
- a differential circuit comprising a third transistor of the first conductive type and a fourth transistor of the first conductive type;
- a current mirror circuit comprising a fifth transistor of a second conductive type and a sixth transistor of the second conductive type, the a fifth gate electrode and a fifth drain region of the fifth transistor being connected to each other;
- a seventh transistor of the first conductive type for electrically connecting the differential circuit and a first current source;
- an eighth transistor of the second conductive type for electrically connecting the fifth transistor and a second current source;
- a ninth transistor of the second conductive type for electrically connecting the sixth transistor and a third current source;
- and
- a power supply portion for supplying potential to gate electrodes of the seventh, eighth, and ninth transistors,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal from the first transistor is input to a third gate electrode of the third transistor,
- wherein a second input signal is input to a second source region of the second transistor, and
- wherein a second output signal from the second transistor is input to a fourth gate electrode of the fourth transistor.
10 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- first and second current mirror circuits;
- a differential circuit electrically connected to the first and second current mirror circuits;
- a first current source for supplying current to the differential circuit;
- a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
- a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
- and
- second and third current sources for supplying current to the first and second transistors, respectively,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal from the first transistor is input to the differential circuit,
- wherein a second input signal is input to a second source region of the second transistor, and
- wherein a second output signal from the second transistor is input to the differential circuit.
8 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- first and second current mirror circuits;
- a differential circuit electrically connected to the first and second current mirror circuits;
- a first current source for supplying current to the differential circuit;
- a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
- a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
- and
- second and third current sources for supplying current to the first and second transistors, respectively,
- wherein the differential circuit comprises third and fourth transistors,
- wherein the first drain region of the first transistor and a third gate electrode of the third transistor are electrically connected to each other,
- wherein a second drain region of the second transistor and a fourth gate electrode of the fourth transistor are electrically connected to each other,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein the a first output signal from the first transistor is input to a third gate electrode of the third transistor;
- wherein a second input signal is input to a second source region of the second transistor, and
- wherein a second output signal from the second transistor is input to a fourth gate electrode of the fourth transistor.
11 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a current mirror circuit;
- a differential circuit having the current mirror circuit as a load;
- a first current source for supplying current to the differential circuit;
- first and second source follower circuits;
- and
- a transistor for reset,
- wherein a first input signal is input to the first source follower circuit,
- wherein a first output signal from the first source follower circuit is input to the differential circuit,
- wherein a second input signal is input to the second source follower circuit,
- wherein a second output signal from the second source follower circuit is input to the differential circuit, and
- wherein current supply by the first current source is blocked by a reset signal input to the transistor for reset, during a period where voltage amplitude of an input signal is not converted.
8 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a current mirror circuit;
- a differential circuit having the current mirror circuit as a load;
- a first current source for supplying current to the differential circuit;
- a first transistor having a first gate electrode and a first drain region being electrically connected to each other;
- a second transistor having a second gate electrode and a second drain region being electrically connected to each other;
- and
- second and third current sources for supplying current to the first and second transistors, respectively,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal from the first transistor is input to the differential circuit,
- wherein a second input signal is input to a second source region of the second transistor,
- wherein a second output signal from the second transistor is input to the differential circuit, and
- wherein current supply by the first, second, and third current sources is blocked during a period where voltage amplitude of an input signal is not converted.
9 more elements
A semiconductor device having a level shifter, the level shifter comprising:
- a first transistor of a first conductive type, having a first gate electrode and a first drain region thereof being connected to each other;
- a second transistor of the first conductive type, having a second gate electrode and a second drain region thereof being connected to each other;
- a differential circuit comprising a third transistor of the first conductive type and a fourth transistor of the first conductive type;
- a current mirror circuit comprising a fifth transistor of a second conductive type having a fifth gate electrode and a fifth drain region being electrically connected to each other, and a sixth transistor of the second conductive type;
- a seventh transistor of the first conductive type for connecting the differential circuit and a first current source;
- an eighth transistor of the second conductive type for electrically connecting the fifth transistor and a second current source;
- a ninth transistor of the second conductive type for electrically connecting the sixth transistor and a third current source;
- a power supply portion for supplying potential to gate electrodes of the seventh, eighth, and ninth transistors;
- a tenth transistor for reset of the second conductive type;
- and
- a eleventh transistor for reset of the first conductive type,
- wherein the first drain region of the first transistor and a third gate electrode of the third transistor are electrically connected to each other,
- wherein the second drain region of the second transistor and a fourth gate electrode of the fourth transistor are electrically connected to each other,
- wherein a tenth source region of the tenth transistor for reset is electrically connected to seventh and eighth source regions of the seventh and eighth transistors, and a tenth drain region of the tenth transistor for reset is electrically connected to seventh and eighth gate electrodes of the seventh and eighth transistors,
- wherein an eleventh source region of the eleventh transistor for reset is electrically connected to a ninth source region of the ninth transistor, and an eleventh drain region of the eleventh transistor for reset is electrically connected to a ninth gate electrode of the ninth transistor,
- wherein a first input signal is input to a first source region of the first transistor,
- wherein a first output signal from the first transistor is input to the third gate electrode of the third transistor,
- wherein a second input signal is input to a second source region of the second transistor,
- wherein a second output signal from the second transistor is input to the fourth gate electrode of the fourth transistor, and
- wherein during a period where voltage amplitude of an input signal is not converted, current supply is blocked by a reset signal input to the tenth and eleventh transistors for reset, and by making the seventh, eighth, and ninth transistors in a nonconductive state.
17 more elements
Dependencies are inferred from the claim text.