US 2004/0201409 A1 · Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them

Abstract

A delay adjusting circuit that can minimize a delay at selectors even when the number of delay stages and the number of selector stages are increased, to enable a stable and speedy operation. As selectors S in a delay producing circuit (11), 2:1 selectors, each of the type that selectively outputs one from two inputs, may be used which are connected to input/output portions of N-stage delay elements D1 to DN for enabling delayed output of an even-stage delayed clock signal (Even) and an odd-stage delayed clock signal (Odd). In this case, the 2:1 selectors are arranged in a two-stage configuration including the for-even-stage selectors (S1, S3, . . . , Sn, S(n+2)) and the for-odd-stage selectors (S2, . . . , S(n+1), S(n+3)). The even-stage delayed clock signal (Even) is obtained through the first-stage selector S1. The odd-stage delayed clock signal (Odd) is obtained through the second-stage selector S2.

Claims9

Dependent claims

A delay producing method using first-stage to Nth-stage delay elements connected in series to each other and, when a clock signal is inputted to an input side of said first-stage delay element, producing an even-stage delayed signal from a clock signal obtained from the even-stage delay element, and an odd-stage delayed signal from a clock signal obtained from the odd-stage delay element, said delay producing method comprising:

using first-stage and second-stage to Nth-stage selectors arranged in one-to-one correspondence with said delay elements, and each outputting one selected from two inputs;
using, as one of inputs to each of said first-stage to Nth-stage selectors, an input to a corresponding one of said delay elements;
using, as the other of the inputs to each of said first-stage to (N−1)th-stage selectors, an output from said selector of the next but one stage;
outputting said even-stage delayed signal from said first-stage selector;
and
outputting said odd-stage delayed signal from said second-stage selector.

3 more elements

A delay producing circuit comprising N-stage delay elements connected in series to each other, and selectors that, in the state where a clock signal is inputted to an input side of the first-stage delay element, switchingly select delays of the given delay elements from input/output portions of said N-stage delay elements in response to a switching control signal from an external control circuit, thereby to output an even-stage delayed clock signal and an odd-stage delayed clock signal,

wherein said selectors are 2:1 selectors each of the type that selectively outputs one from two inputs, and include for-even-stage selectors connected in series to each other so as to successively receive, as one input sequence, an output from the input side of said first-stage delay element and outputs from output sides of the second-stage to (N−1)th-stage delay elements, said outputs each received from every other one of said input/output portions of said N-stage delay elements, and further receive, as the other input sequence, outputs from the second-stage and subsequent selectors at the prior-stage selectors, respectively, thereby to enable said even-stage delayed clock signal obtained by the selector of the stage switchingly selected by said switching control signal, to be outputted through the first-stage selector, and further include for-odd-stage selectors connected in series to each other so as to successively receive, as one input sequence, an output from an output side of said first-stage delay element, and outputs from output sides of the third-stage to Nth-stage delay elements, said outputs each received from every other one of said input/output portions of said N-stage delay elements, and further receive, as the other input sequence, outputs from the second-stage and subsequent selectors at the prior-stage selectors, respectively, thereby to enable said odd-stage delayed clock signal obtained by the selector of the stage switchingly selected by said switching control signal, to be outputted through the first-stage selector.

Dependencies are inferred from the claim text.

Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them

Life of this patent

Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them

Life of this patent

Abstract

Claims9