Delay locked loop and a method for delay control

A delay lock loop apparatus for use with an externally generated clock signal comprising:

• a delay device comprising a first delay element and a second delay element, wherein the first delay element is configured to generate a first output responsive to a control signal and a first input, and wherein the second delay element is configured to generate the first input responsive to the externally generated clock signal and a set signal related to the frequency of the externally generated clock signal,
• a feedback device operably connected to the first delay element and configured to generate a time delayed first output,
• a phase difference detection device configured to generate signal responsive to the phase difference between the time delayed first output and the externally generated clock signal, and
• a frequency detection unit configured to generate the set signal responsive to the frequency of the externally generated clock signal.

A method of providing clock signals to a circuit, the method comprising the steps of:

• providing a delay control apparatus comprising a first variable delay element and at least one frequency variable delay element,
• detecting the frequency of an external clock signal,
• adjusting the time delay of the at least one frequency variable delay element based upon the frequency of the external clock signal,
• delaying the external clock signal with the at least one frequency variable delay element and providing the delayed external clock signal to the first variable delay element,
• further delaying the delayed external clock signal with the first variable delay element,
• providing the further delayed external clock signal to a feedback device,
• time delaying the further delayed external clock signal with the feedback device,
• detecting the phase difference between the time delayed external clock signal and the external clock signal,
• generating a control signal based upon the detected phase difference, and
• controlling the time delay of the first variable delay element with the control signal so as to reduce the detected phase difference.