Ring-resister controlled DLL with fine delay line and direct skew sensing detector

A ring-register controlled delay locked loop comprising:

• a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model;
• a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the external clock signal with the output clock signal;
• a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means;
• a coarse delay means having a plurality of unit delayers which are coupled each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means;
• an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means;
• and
• a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

A ring-register controlled delay locked loop comprising:

• a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model;
• a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the internal clock signal with the output clock signal;
• a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means;
• a coarse delay means having a plurality of unit delayers which are coupled each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means;
• an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means;
• and
• a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

A ring-register controlled delay locked loop comprising:

• a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model;
• a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the external clock signal with the output clock signal;
• a coarse delay means having a plurality of unit delayers which are coupled each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal;
• an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means;
• a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal;
• and
• a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

A ring-register controlled delay locked loop comprising:

• a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model;
• a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the internal clock signal with the output clock signal;
• a coarse delay means having a plurality of unit delayers which are coupled each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal;
• an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means;
• a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal;
• and
• a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

A ring-register controlled delay locked loop comprising:

• a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal;
• a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group;
• a first control means for determining an amount of lineal delay in the first delay group;
• and
• a second control means for determining an amount of circular delay in the first delay group.

Aring-register controlled delay locked loop comprising:

• a first delay group including at least one unit delay element for delaying an input clock signal
• a phase modifying means for modifying an output signals from the first delay group;
• a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group;
• a first control means for determining an amount of lineal delay in the first delay group;
• and
• a second control means for determining an amount of circular delay in the second delay group.