Topology for providing clock signals to multiple circuit units on a circuit module
OwnerAbdallah Bacha, Maksim Kuzmenka +2inventors
InventorsAbdallah Bacha, Maksim Kuzmenka, Simon Muff, Siva Raghuram
Life of this patent
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Abstract
A circuit module has a circuit board, multiple circuit units on the circuit board and at least one clock input on the circuit board for receiving an external clock signal. The circuit module has a first PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.
Claims21
A circuit module comprising:
- a circuit board;
- multiple circuit units on the circuit board;
- at least one clock input on the circuit board for receiving an external clock signal;
- a first phase locked loop (PLL) unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units;
- and
- a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.
A memory module comprising:
- a circuit board;
- multiple memory chips on the circuit board;
- a clock input on the circuit board for receiving an external clock signal;
- a first phase locked loop (PLL) unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the memory chips;
- and
- a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the memory chips.
A circuit module comprising:
- a circuit board;
- a plurality of memory chips arranged along the width of the circuit board comprising a first set of memory chips and a second set of memory chips;
- at least one clock input on the circuit board for receiving an external clock signal;
- a first phase locked loop (PLL) unit arranged within the first set of memory chips for providing an internal clock signal based on the external clock signal to at least a first one of the memory chips;
- and
- a second PLL unit arranged within said second set of memory chips for providing an internal clock signal based on the external clock signal to at least a second one of the memory chips.
Dependencies are inferred from the claim text.