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US 2004/0201404 A1Published application
Power-on-reset circuit based on the threshold levels and quadratic I-V behavior of MOS transistors
AssigneeMicron Technology, Inc.
InventorAlf Olsen
Life of this patent
Estimating the term…
Abstract
A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage levels where the power-on-reset circuit behavior reverses (which controls the reset signal) is determined by the dimensions of the transistors selected for the voltage dividers. The system and method described allows for a clock-independent stable power-up phase wile consuming a very small area of a circuit board and, in particular, on integrated circuits.
Claims59
A clock-independent power-on-reset circuit comprising:
- a first voltage divider connected to a supply voltage;
- a second voltage divider connected to said supply voltage;
- an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to a first one of a coupled pair of asymmetrical inverters, wherein said high gain amplifier in open loop mode operates as a comparator;
- and
- a feedback circuit for feeding back an output of the amplifier to an input of the amplifier.
2 more elements
A method of operating a power-on-reset circuit, the method comprising:
- applying a first output generated by a first voltage divider to an inverting input of a differential stage of an amplifier while concurrently applying a second output generated by a second voltage divider to a non-imverting input of said differential stage;
- applying a third output generated by said differential stage of said amplifier to a first asymmetrical inverter of a pair of asymmetrical inverters of said amplifier;
- feeding back a signal generated by said amplifier to said non-inverting input of said amplifier;
- and
- outputting a reset signal generated by a second asymmetrical inverter of said pair of asymmetrical inverters.
2 more elements
A clock-independent power-on-reset circuit, comprising:
- a first voltage divider connected to a supply voltage;
- a second voltage divider connected to said supply voltage;
- an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said first and second voltage dividers respectively;
- and
- a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier.
2 more elements
A processor circuit comprising:
- a clock-independent power-on-reset circuit, said clock-independent power-on-reset circuit further comprising:
- a first voltage divider connected to a supply voltage;
- a second voltage divider connected to said supply voltage;
- an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to a first one of a coupled pair of asymmetrical inverters, wherein said high gain amplifier in open loop mode operates as a comparator;
- and
- a feedback circuit for feeding back an output of the amplifier to an input of the amplifier.
3 more elements
A method of operating a power-on-reset circuit comprising the steps of:
- setting a reset signal to a logical first state when a supply voltage is below a first predefined level;
- and
- setting said reset signal to a logical second state when the supply voltage is above a second predefined level.
A processor circuit comprising:
- a clock independent power-on reset circuit comprising:
- a first voltage divider connected to a supply voltage;
- a second voltage divider connected to said supply voltage;
- an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said first and second voltage dividers respectively;
- and
- a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier.
3 more elements
A clock independent power-on-reset circuit comprising:
- a first voltage divider coupled to a supply voltage;
- a second voltage divider coupled to said supply voltage;
- a comparison circuit having:
- a non-inverting input for receiving an output voltage from said first voltage divider;
- an inverting input for receiving an output voltage from said second voltage divider;
- a circuit for comparing the output voltages received at said non-inverting and inverting inputs and providing a status signal representative of which of said output voltages is higher;
- and
- an output circuit for providing a power-on-reset signal in response to said status signal of said comparison circuit.
5 more elements
A processing circuit comprising:
- a clock independent power-on reset circuit farther comprising:
- a first voltage divider coupled to a supply voltage;
- a second voltage divider coupled to said supply voltage;
- a comparison circuit having:
- a non-inverting input for receiving an output voltage from said first voltage divider;
- an inverting input for receiving an output voltage from said second voltage divider;
- a circuit for comparing the output voltages received at said non-inverting and inverting inputs and providing a status signal representative of which of said output voltages is higher;
- and
- an output circuit for providing a power-on-reset signal in response to said status signal of said comparison circuit.
6 more elements
A clock-independent power-on-reset circuit comprising:
- an NMOS voltage divider connected to a supply voltage;
- a PMOS voltage divider connected to said supply voltage;
- an amplifier coupled to said NMOS and said PMOS voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to a first one of a coupled pair of asymmetrical inverters, wherein said high gain amplifier in open loop mode operates as a comparator;
- a second pair of coupled asymmetrical inverters, said first and second pair of asymmetrical inverters coupled to each other;
- and
- a feedback circuit for feeding back an output of the amplifier to an input of the amplifier.
3 more elements
Dependencies are inferred from the claim text.