Superconductor ballistic RAM
AssigneeNorthrop Grumman Corporation
InventorQuentin P. Herr
Life of this patent
Estimating the term…
Abstract
A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.
Claims18
A superconductor memory array, comprising:
- memory cells arranged in a row-column format, each of the memory cells including a storage loop with a Josephson junction for storing a binary value;
- row address lines each being magnetically coupled in series to a row of the memory cells;
- column address lines each being connected in series to a column of the memory cells;
- and
- sense amplifiers each being located on one of the column address lines for sensing state changes in the memory cells located in columns of the memory cells during a READ operation initiated by row address line READ signals.
A superconductor memory cell configuration, comprising:
- memory cells arranged in a column, each of the memory cells including a storage loop with a Josephson junction for storing a binary value;
- a column address line for connecting the memory cells in series;
- and
- a sense amplifier located on the column address line for sensing state changes in the memory cells during a READ operation.
A superconductor memory configuration, comprising:
- a memory cell including:
- a storage loop including a Josephson junction for storing a binary value;
- a row address line input magnetically coupled to the storage loop for receiving a READ voltage signal to initiate a READ operation;
- a column address line input connected to the Josephson junction for receiving a series of SFQ pulses, for outputting all of the series of SFQ pulses if an internal persistent loop current does not change direction during the READ operation, and for outputting fewer than all of the series of SFQ pulses if the internal persistent loop current changes direction during the READ operation;
- a bridge resistor arranged in parallel with the Josephson junction for damping the Josephson junction;
- and
- a non-dedicated sense amplifier for receiving all of the series of SFQ pulses if the internal persistent loop current does not change direction during the READ operation, for receiving the fewer than all of the series of SFQ pulses if the internal persistent loop current changes direction during the READ operation, and for outputting a signal indicative of the binary value stored in the storage loop based on how many of the series of SFQ pulses are received.
Dependencies are inferred from the claim text.