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US 2004/0201397 A1Published application
Method and apparatus for die testing on wafer
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
Integrated circuit die on wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the wafer.
Claims2
A semiconductor wafer, comprising:
- an integrated circuit die including functional circuitry for performing normal operating functions of the integrated circuit die, a plurality of bond pads coupled to said functional circuitry, a first said bond pad provided to receive a control signal, and circuitry responsive to said control signal to permit a signal received at a second said bond pad to pass through said integrated circuit die from said second bond pad to a third said bond pad along a test path which connects said second and third bond pads and which is isolated from said functional circuitry;
- and
- a further integrated circuit die connected to said third bond pad to receive a test signal via said test path.
A method of testing an integrated circuit die on a semiconductor wafer having a plurality of integrated circuit die, comprising the steps of:
- connecting first and second bond pads of a first integrated circuit die to provide a test path through the first die;
- and
- applying a test signal to a second integrated circuit die connected to the second bond pad of the first die, including the step of passing the test signal from the first bond pad of the first die along the test path through the first die to the second bond pad of the first die.
Dependencies are inferred from the claim text.