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US 2004/0201093 A1Published application
Evaluating pattern for measuring and erosion of a semiconductor wafer polished by a chemical mechanical polishing
AssigneeOki Electric Industry Co., Ltd.
InventorTadashi Narita
Life of this patent
Estimating the term…
Abstract
An evaluating pattern includes a conductive pattern formed on a substrate, an insulating layer which is formed on the conductive pattern, a plurality of contact holes formed in a rectangular area through the insulating layer, and a conductive material filled into the contact holes to the conductive pattern.
Claims21
1-8 (Canceled)
9:
- An evaluating pattern comprising:
- a semiconductor substrate:
- an insulating layer formed on the semiconductor substrate;
- a plurality of contact holes formed through the insulating layer in a rectangular area;
- and
- a conductive material filled into the contact holes, wherein the insulating layer has a first thickness in the rectangular area and has a second thickness greater than the first thickness in another area that does not include contact holes.
3 more elements
10:
- An evaluating pattern according to claim 9, wherein distances between the contact holes are substantially equal.
11:
- An evaluating pattern according to claim 9, wherein the insulating layer is formed of silicon oxide.
12:
- An evaluating pattern according to claim 9, wherein the evaluating pattern is formed on a grid line of the semiconductor substrate.
13:
- An evaluating pattern according to claim 9, wherein the semiconductor substrate has a conductive pattern formed in the rectangular area.
14:
- An evaluating pattern according to claim 9, wherein the conductive material includes at least one of tungsten, titanium and titanium nitride.
15:
- An evaluating pattern according to claim 9, wherein a density of the contact holes in the rectangular area is set to correspond to a density of an area in a chip region of the semiconductor substrate which has a greatest density of contact holes.
16:
- An evaluating pattern according to claim 15, wherein the density of the contact holes in the rectangular area is about 25%.
17:
- An evaluating pattern comprising:
- a semiconductor substrate having a first rectangular area, a second rectangular area surrounding the first rectangular area and a peripheral area surrounding the second rectangular area;
- an insulating layer formed on the semiconductor substrate;
- a plurality of contact holes formed through the insulating layer in the second rectangular area, and not in the first rectangular area and the peripheral area;
- and
- a conductive material filled into the contact holes, wherein the insulating layer has a first thickness in the first rectangular area, a second thickness that is less than the first thickness in the second rectangular area, and a third thickness that is greater than the first thickness in the peripheral area.
3 more elements
18:
- An evaluating pattern according to claim 17, wherein distances between the contact holes are substantially equal.
19:
- An evaluating pattern according to claim 17, wherein the insulating layer is formed of silicon oxide.
20:
- An evaluating pattern according to claim 17, wherein the evaluating pattern is formed on a grid line of the semiconductor substrate.
21:
- An evaluating pattern according to claim 17, wherein the semiconductor substrate has a conductive pattern formed in the second rectangular area.
22:
- An evaluating pattern according to claim 17, wherein the conductive material includes at least one of tungsten, titanium and titanium nitride.
23:
- An evaluating pattern according to claim 17, wherein a density of the contact holes in the second rectangular area is set to correspond to a density of an area in a chip region of the semiconductor substrate which has a greater density of contact holes.
24:
- An evaluating pattern according to claim 23, wherein the density of the contact holes is about 25%.
25:
- An evaluating pattern according to claim 17, wherein the first rectangular area has a width of about 50 μm.
26:
- An evaluating pattern according to claim 17, wherein the second rectangular area has a width of about 100 μm.
27:
- An evaluating pattern comprising:
- a semiconductor wafer having a plurality of chip regions and a grid line region separating the chip regions;
- an insulating layer formed on the semiconductor wafer;
- a plurality of contact holes formed through the insulating layer in a rectangular area;
- and
- a conductive material filled into the contact holes, wherein the insulating layer has a first thickness in the rectangular area and has a second thickness greater than the first thickness in an area that does not include contact holes.
3 more elements
28:
- An evaluating pattern according to claim 27, wherein the insulating layer is formed of silicon oxide.