Semiconductor multi-chip package and fabrication method
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Kuk Kim, Chang-Cheol Lee
Life of this patent
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Abstract
A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.
Claims58
A multi-chip package, comprising:
- a package substrate having bond fingers disposed thereon;
- a first chip having first bonding pads on a substantially center portion thereof, the first chip disposed on the package substrate;
- insulating support structures formed on the first chip located outward of the first bonding pads;
- a bonding wire connected between one of the bond fingers and at least one of the first bonding pads;
- and
- a second chip having second bonding pads disposed over the bonding wire and overlying the insulating support structures.
A multi-chip package, comprising:
- a package substrate having bond fingers disposed thereon;
- a first chip having first bonding pads on a substantially center portion thereof, the first chip disposed on the package substrate;
- insulating support structures formed on the first chip located outward of the first bonding pads;
- a bonding wire connected between one of the bond fingers and at least one of the first bonding pads, the bonding wire spaced apart from the first chip by the support structures;
- and
- a second chip stacked over the bonding wire and overlying the insulating support structures;
- and
- an insulating interposer sandwiched between the first chip and the second chip.
A multi-chip package, comprising:
- a package substrate;
- a first chip mounted on the package substrate, the first chip having center bonding pads on a substantially center portion thereof;
- a second chip stacked on the first chip, the second chip electrically connected to the package substrate;
- and
- bonding wires electrically connected between the package substrate and the center bonding pads.
A method of forming a multi-chip package, the method comprising:
- providing a package substrate;
- mounting a first chip on the package substrate, the first chip having center bonding pads on a substantially center portion thereof;
- electrically interconnecting the package substrate and at least one of the center bonding pads using a bonding wire;
- and
- stacking a second chip over the first chip.
A method of forming a multi-chip package, the method comprising:
- providing a package substrate having bond fingers disposed thereon;
- mounting a first chip on the package substrate, the first chip having center bonding pads on a substantially center portion thereof;
- forming insulating support structures on the first chip located outward of the center bonding pads;
- electrically connecting one of the bond fingers with at least one of the center bonding pads using a bonding wire;
- and
- stacking a second chip over the bonding wire and overlying the insulating support structures.
A wafer level packaging method, comprising:
- providing a wafer having integrated circuit chips, the chips having center bonding pads on a substantially center portion thereof;
- forming insulating support structures on at least one of the chips, the insulating support structures located outward of center bonding pads;
- and
- singulating the chips.
Dependencies are inferred from the claim text.