Stack package made of chip scale packages
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Ho Lee
Life of this patent
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Abstract
A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.
Claims20
A stack package including two or more area array type chip scale packages, each chip scale package comprising:
- a substrate;
- a plurality of ball land pads formed on a lower surface of the substrate;
- a plurality of circuit patterns formed on the lower surface of the substrate and electrically connected to the ball land pads;
- and
- one or more chips installed on an upper surface of the substrate and electrically connected to the circuit patterns,
- wherein each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner where the ball land pads of the upper stacked chip scale package face in the opposite direction as the ball land pads of the lower stacked chip scale packages, and wherein the circuit patterns of the upper stacked chip scale package are electrically connected to those of the lower stacked chip scale package.
A method of forming a stack package of two or more area array type chip scale packages, the method comprising:
- forming a lower chip scale package of an adjacent pair of chip scale packages including a substrate, a plurality of ball land pads and circuit patterns formed on a lower surface of the substrate, and one or more chips formed on an upper surface of the substrate;
- forming an upper chip scale package of the adjacent pair of chip scale packages in the same manner as the lower chip scale package;
- attaching the upper chip scale package to the lower chip scale package so that the ball land pads of the upper chip scale package face the opposite direction as the ball land pads of the lower chip scale package;
- and
- electrically connecting the circuit patterns of the upper chip scale package to the circuit patterns of the lower chip scale package.
The method according to claim 16, further comprising bending the ends of the connecting boards to attach to a larger surface of the connection pads.
Dependencies are inferred from the claim text.