Hard-macro and semiconductor integrated circuit including the same

A semiconductor integrated circuit including a hard-macro arranged on a semiconductor chip for constituting a part of said semiconductor integrated circuit, including at least one wire passing therethrough, wherein said wire is formed in said hard-macro before said hard-macro is arranged on said semiconductor chip, and said wire starts a first outer edge of said hard-macro and terminates at a second outer edge of said hard-macro intersecting with said first outer edge.

A floor-planner including a device for analyzing a floor-plan of a semiconductor integrated circuit including a hard-macro arranged on a semiconductor chip for constituting a part of said semiconductor integrated circuit which hard-macro includes at least one wire passing therethrough, wherein said wire is formed in said hard-macro before said hard-macro is arranged on said semiconductor chip, and said wire starts a first outer edge of said hard-macro and terminates at a second outer edge of said hard-macro intersecting with said first outer edge.

A program for causing a computer to analyze a floor-plan of a semiconductor integrated circuit, wherein said semiconductor integrated circuit includes a hard-macro arranged on a semiconductor chip for constituting a part of said semiconductor integrated circuit which hard-macro includes at least one wire passing therethrough, wherein said wire is formed in said hard-macro before said hard-macro is arranged on said semiconductor chip, and said wire starts a first outer edge of said hard-macro and terminates at a second outer edge of said hard-macro intersecting with said first outer edge.