CMOS pixel using vertical structure and sub-micron CMOS process

A CMOS pixel structure, comprising:

• a substrate formed of P type epitaxial silicon;
• a first N well, formed of N type silicon, in said substrate, wherein said first N well is a distance below the top surface of said substrate;
• a second N well formed of N type silicon in said substrate, wherein the top surface of said second N well is the top surface of said substrate and said second N well has an inner periphery and an outer periphery;
• an overlap region of N type silicon between said first N well and said second N well connecting said first N well to said second N well;
• a P well formed of P type silicon within the inner periphery of said second N well and between the top surface of said substrate and said first N well;
• a first N+ region formed of N+ type silicon in said P well, wherein the top surface of said substrate forms the top surface of said first N+ region;
• a second N+ region formed of N+ type silicon formed in said P well, wherein the top surface of said substrate forms the top surface of said second N+ region;
• and
• a first P+ region, formed of P+ type silicon in said second N well, wherein the top surface of said substrate forms the top surface of said first P+ region.

A pixel circuit, comprising:

• a P type substrate connected to ground potential;
• an N well formed in said P type substrate, wherein the PN junction between said N well and said P type substrate forms a first diode;
• a P well formed in said N well wherein a part of said N well lies below said P well and the PN junction between said P well and said N well forms a second diode;
• a PMOS transistor formed in said N well, wherein the drain of said PMOS transistor is connected to ground potential;
• a first NMOS transistor formed in said P well wherein the drain of said first NMOS transistor is connected to a high potential, VDD;
• a second NMOS transistor wherein the drain of said second NMOS transistor is connected to the source of said first NMOS transistor;
• a third NMOS transistor wherein the source of said third NMOS transistor is connected to the source of said PMOS transistor;
• a third diode connected between said N well and a first reset voltage node, wherein the anode of said third diode is connected to said N well and the cathode of said third diode is connected to said first reset voltage source;
• and
• a fourth diode connected between said P well and a second reset voltage node, wherein the cathode of said third diode is connected to said P well and the anode of said third diode is connected to said second reset voltage source.