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US 2004/0201070 A1Published application
Self-aligned, low-resistance, efficient MRAM read/write conductors
AssigneeMicron Technology, Inc.
InventorJames G. Deak
Life of this patent
Estimating the term…
Abstract
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.
Claims95
A method of forming at least one magnetoresistive random access memory cell structure, the method comprising:
- forming a trench in a first insulating layer to define a first upper level and a second lower level, said first level and said second level being connected by at least a sidewall region;
- forming a ferromagnetic cladding layer within said trench and over said second level and said sidewall region of said first insulating layer;
- forming a first conductive layer within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- forming a second insulating layer within said trench and over a second level and a sidewall region of said first conductive layer;
- forming a second conductive layer within said trench;
- and
- forming a magnetic tunnel junction element over said second conductive layer.
4 more elements
A method of forming at least one magnetoresistive random access memory cell structure, the method comprising:
- forming a trench in a first insulating layer to define a first upper level and a second lower level, said first level and said second level being connected by at least a sidewall region;
- forming a ferromagnetic cladding layer within said trench and over said second level and said sidewall region of said first insulating layer;
- forming a first conductive layer within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- forming a second insulating layer within said trench and over a second level and a sidewall region of said first conductive layer;
- forming a third insulating layer over said first upper level of said first insulating layer, and within said trench and over a second level and a sidewall region of said second insulating layer;
- forming a second conductive layer within said trench;
- and
- forming a magnetic tunnel junction element over said second conductive layer.
5 more elements
At least one magnetoresistive random access memory cell structure, comprising:
- a trench in a first insulating layer defining a first upper level and a second lower level, said first level and said second level being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within said trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a second conductive layer formed within said trench;
- and
- a magnetic tunnel junction element formed over said second conductive layer.
4 more elements
At least one magnetoresistive random access memory cell structure, comprising:
- a trench in a first insulating layer defining a first upper level and a second lower level, said first level and said second level being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within said trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a third insulating layer formed over said first upper level of said first insulating layer, and within said trench and over a second lower level and a sidewall region of said second insulating layer;
- a second conductive layer formed within said trench;
- and
- a magnetic tunnel junction element formed over said second conductive layer.
5 more elements
A processor system, comprising:
- a processor;
- a plurality of trenches formed in a first insulating layer, each of said plurality of trenches defining a first upper level and a second lower level, said first level and second level being connected by at least a sidewall region;
- a ferromagnetic cladding layer formed within a trench and over said second level and said sidewall region of said first insulating layer;
- a first conductive layer formed within said trench and over a second level and a sidewall region of said ferromagnetic cladding layer;
- a second insulating layer formed within said trench and over a second level and a sidewall region of said first conductive layer;
- a third insulating layer formed over said first upper level of said first insulating layer, and within said trench and over a second lower level and a sidewall region of said second insulating layer;
- a second conductive layer formed within said trench;
- a magnetic tunnel junction element formed over said second conductive layer, such that a plurality of magnetic tunnel junctions form rows;
- and
- an interconnect line disposed above each of said plurality of magnetic tunnel junction elements.
7 more elements
Dependencies are inferred from the claim text.