Nonvolatile memories with a floating gate having an upward protrusion

A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:

• forming a first structure overlying the semiconductor substrate, the first structure comprising:
• a first conductive gate of a nonvolatile memory cell;
• and
• a first dielectric over a sidewall of the first conductive gate;
• forming a layer (“FG layer”) to provide a conductive floating gate for the memory cell, wherein the FG layer comprises first and second sub-layers, and wherein forming the FG layer comprises:
• forming the first sub-layer to provide a first portion of the floating gate, the first structure protruding above the first sub-layer;
• forming the second sub-layer layer and etching the second sub-layer to form a second portion of the floating gate on the sidewall of the first structure;
• forming a second dielectric over the first and second sub-layers;
• forming a second conductive gate for the memory cell on the second dielectric.

A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:

• forming a first structure over a semiconductor substrate, the first structure comprising:
• a first conductive gate of a nonvolatile memory cell;
• and
• a first dielectric over the first conductive gate;
• forming a layer (“FG layer”) to provide a conductive floating gate for the memory cell, wherein the floating gate comprises a first portion and an upward protruding second portion, the second portion being formed over the first dielectric over at least a sidewall of the first conductive gate;
• forming a second dielectric over the FG layer;
• forming a layer G2 over first structure, the FG layer, and the second dielectric, to provide a second conductive gate for the memory cell, the layer G2 having a portion P1 protruding above the first structure;
• forming a layer L1 over the layer G2 such that the protruding portion P1 of the layer G2 is exposed and not completely covered by the layer L1;
• partially removing the layer G2 selectively to the layer L1 to form a cavity at the location of the portion P1;
• forming a layer L2 at least in the cavity;
• removing at least a part of the layer L1 and the layer G2 selectively to the layer L2.

A method for manufacturing an integrated circuit comprising a nonvolatile memory comprising nonvolatile memory cells, the method comprising:

• forming one or more substrate isolation regions in a semiconductor substrate;
• forming one or more first structures over the semiconductor substrate, each first structure comprising:
• a conductive line G1, wherein each memory cell comprises a first conductive gate comprising a portion of a line G1;
• and
• a first dielectric over the lines G1;
• forming a layer (“FG layer”) to provide a conductive floating gate for each memory cell, wherein each floating gate comprises a first portion and an upward protruding second portion, the second portion being formed on the first dielectric and overlaying at least a sidewall of a line G1;
• patterning the FG layer through a mask opening or openings to remove portions of the FG layer between different memory cells, wherein all edges of the mask openings in memory cell areas are positioned over the lines G1 and/or the substrate isolation regions.

An integrated circuit comprising:

• a semiconductor substrate;
• a first dielectric region on the semiconductor substrate;
• a first conductive gate of a nonvolatile memory cell on the first dielectric region;
• a second dielectric region of the memory cell on the semiconductor substrate;
• a conductive floating gate of the memory cell on the second dielectric region, the floating gate comprising a first portion and an upward protruding second portion, wherein in any horizontal cross section by a plane passing through the upward protruding second portion and the first conductive gate, the distance between the upward protruding second portion and the first conductive gate is smaller than the width of the first conductive gate;
• a second conductive gate overlying at least a portion of the floating gate but not overlying the first conductive gate;
• a dielectric insulating the floating gate from the first and second conductive gates, and insulating the first conductive gate from the second conductive gate.

An integrated circuit comprising:

• a semiconductor substrate;
• a first dielectric region on the semiconductor substrate;
• a first conductive gate of a nonvolatile memory cell on the first dielectric region;
• a second dielectric region of the memory cell on the semiconductor substrate;
• a conductive floating gate of the memory cell on the second dielectric region;
• a second conductive gate overlying a portion of the floating gate, wherein the top of the second conductive gate is not higher than the top of the floating gate;
• a dielectric insulating the floating gate from the first and second conductive gates, and insulating the first conductive gate from the second conductive gate.

An integrated circuit comprising:

• a semiconductor substrate;
• a first structure overlying the semiconductor substrate, the first structure comprising:
• a first conductive gate of a nonvolatile memory cell;
• and
• a first dielectric on a sidewall of the first conductive gate;
• a conductive floating gate of the memory cell on the second dielectric region, the floating gate comprising an upward protrusion formed as a spacer on a sidewall of the first dielectric;
• a second conductive gate overlying at least a portion of the floating gate but not overlying the first conductive gate, wherein the upward protrusion of the floating gate is between the first and second conductive gates;
• a dielectric insulating the floating gate from the second conductive gate.

An integrated circuit comprising:

• a semiconductor substrate;
• a first dielectric region on the semiconductor substrate;
• a first conductive gate of a nonvolatile memory cell on the first dielectric region;
• a second dielectric region of the memory cell on the semiconductor substrate;
• a conductive floating gate of the memory cell on the second dielectric region, the floating gate comprising an upward protrusion at an edge of the floating gate adjacent to the first conductive gate but not at an opposite edge of the floating gate;
• a second conductive gate overlying at least a portion of the floating gate but not overlying the first conductive gate, wherein the upward protrusion of the floating gate is between the first and second conductive gates;
• a dielectric insulating the floating gate from the first and second conductive gates, and insulating the first conductive gate from the second conductive gate.