DRAM array, method of manufacturing a DRAM array, and computer system

A method of forming an approximately 6F2 DRAM array, comprising:

• defining a first memory cell;
• defining a second memory cell;
• forming an isolation gate between the first and second memory cells to provide electrical isolation therebetween;
• and
• defining a first switch having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a stress voltage.

A method of forming memory cells in an approximately 6F2 DRAM array including:

• forming a first memory cell;
• forming a second memory cell adjacent the first memory cell;
• forming an isolation gate between the first and second memory cells and configured to provide electrical isolation therebetween;
• and
• forming a first switch having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a stress voltage.

A method of stress testing an isolation gate formed between two rows of memory cells in an approximately 6F2 DRAM array comprising:

• turning OFF a first transistor coupled between the isolation gate and a first potential;
• turning ON a second transistor coupled between the isolation gate and a stress potential;
• waiting for a predetermined interval;
• turning the second transistor OFF;
• turning the first transistor ON;
• and
• testing the DRAM array.

A method of isolating a single row of memory cells in an approximately 6F2 DRAM array comprising:

• providing pairs of rows of memory cells;
• providing an isolation gate separating rows comprising each pair of rows, each isolation gate being configured to isolate one of the pair of rows from another of the pair of rows;
• and
• providing a transistor having a load electrode coupled to the isolation gate, the transistor being configured to supply a predetermined voltage to the isolation gate to isolate one of the pair of rows from another of the pair of rows in response to a control signal.

A computer system comprising:

• a central processing unit;
• an input interface coupled to the central processing unit;
• and
• a memory device coupled to the central processing unit, the memory device being configured to store instructions and data for use by the central processing unit, wherein the memory device includes a DRAM array including:
• a first memory cell having an area less than 6F2;
• a second memory cell having an area less than 6F2;
• an isolation gate between the first and second memory cells and configured to provide electrical isolation therebetween;
• and
• a first switch having first and second load electrodes and a control electrode configured to accept a control signal, the first load electrode being coupled to the isolation gate and the second load electrode being configured to be coupled to a voltage source, wherein F is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus a width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array.