Embedded DRAM for metal-insulator-metal (MIM) capacitor structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu
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Abstract
A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.
Claims22
1-32. (canceled)
An embedded DRAM and capacitor structure device comprising:
- trenched capacitors in two twisted trenches through an insulating layer in a memory area of an integrated circuit wherein said two twisted trenches are mirror images of each other and wherein each capacitor in a first of said two twisted trenches is horizontally aligned with a capacitor in a second of said two twisted trenches to form pairs of capacitors wherein said pairs of capacitors are separated from each other horizontally by a first or a second distance wherein said first distance is greater than said second distance;
- a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two twisted trenches and in a horizontal line with one capacitor pair wherein said one capacitor pair has said first separation distance and adjacent capacitor pairs have said second separation distance;
- and
- first line metal contacts in a logic area of said integrated circuit;
- wherein said bit line contact and said first line metal contacts are no higher vertically than said trenched capacitors.
A DRAM structure comprising:
- trenched capacitors in a trench through an insulating layer in a memory area, wherein each of said trenched capacitors comprises a bottom electrode lining an opening in said insulating layer, a capacitor dielectric layer disposed on said bottom electrode, and a top electrode disposed on said capacitor dielectric layer wherein an opening remains in said top electrode within said trench;
- and
- a conductive line disposed on said top electrodes and filling inside said opening and said trench continuously wherein said conductive line is no higher vertically than said top electrode.
A DRAM structure, comprising:
- trenched capacitors in two trenches through an insulating layer in a memory area;
- and
- two conductive lines filling said two trenches respectively and continuously in contact with said trenched capacitors;
- and
- a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two trenches;
- wherein said bit line contact is no higher vertically than said trench capacitors.
An embedded DRAM and capacitor structure device, comprising:
- trenched capacitors in two trenches through an insulating layer in a memory area of an integrated circuit;
- a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two trenches;
- and
- first line metal contacts in a logic area of said integrated circuit;
- wherein said bit line contact and said first line metal contacts are no higher vertically than said trenched capacitors.
Dependencies are inferred from the claim text.