Method of fabricating vertical integrated circuits
AssigneeReveo, Inc.
InventorSadeg M. Faris
Life of this patent
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Abstract
A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.
Claims24
A method of fabricating a vertically integrated circuit, the method comprising the steps of:
- providing a bulk substrate;
- selectively creating strong bond regions and weak bond regions on said substrate;
- providing a first bonded semiconductor layer vertically supported on said substrate;
- creating semiconductor device portions on said first bonded semiconductor layer, said semiconductor device portions corresponding to said weak bond regions;
- removing said first semiconductor layer from said bulk substrate;
- and
- bonding said first semiconductor layer to a second semiconductor layer.
The method of clam 1 further comprising the step of interconnecting said first semiconductor layer with said second semiconductor layer.
A vertical integrated circuit comprising:
- a bulk substrate on a wafer;
- a first selectively bonded semiconductor layer vertically supported on said substrate, said bonded semiconductor layer containing weak bond regions and strong bond regions;
- a second selectively bonded semiconductor layer vertically supported on said first selectively bonded semiconductor layer;
- wherein a semiconductor device portion is created at or on said weak bond regions, and
- wherein said semiconductor device portion vertically spans said first selectively bonded semiconductor layer and said second selectively bonded semiconductor layer.
A vertical integrated circuit formed on a die comprising:
- a bulk substrate on a wafer;
- a first selectively bonded semiconductor layer vertically supported on said substrate, said bonded semiconductor layer containing weak bond regions and strong bond regions;
- a second selectively bonded semiconductor layer vertically supported on said first selectively bonded semiconductor layer;
- wherein a semiconductor device portion is created at or on said weak bond regions;
- wherein said semiconductor device portion vertically spans said first selectively bonded semiconductor layer and said second selectively bonded semiconductor layer, and
- wherein said die is formed by dicing said bonded semiconductor layers.
Dependencies are inferred from the claim text.