Built-in self-test for digital transmitters
AssigneeArrayComm, Inc.
InventorsVeerendra Bhora, Tibor Boros, Pulakesh Roy
Life of this patent
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Abstract
The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes an input buffer to store a digital test sequence, a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence, a test buffer coupled to the modulator to receive and store a representation of the sample sequence, and a test buffer output to enable the test buffer contents to be compared to a reference sequence.
Claims60
An integrated circuit comprising:
- an input buffer to store a digital test sequence;
- a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence;
- a test buffer coupled to the modulator to receive and store a representation of the sample sequence;
- and
- a test buffer output to enable the test buffer contents to be compared to a reference sequence.
A method comprising:
- storing a digital test sequence in an integrated circuit;
- generating a modulated digital sample sequence using a digital data modulator of the integrated circuit based on the test sequence;
- buffering a representation of the sample sequence on the integrated circuit;
- and
- comparing the buffered representation to a reference sequence.
A machine-readable medium having stored thereon data representing instructions which, when executed by a machine, cause the machine to perform operations comprising:
- storing a digital test sequence in an integrated circuit;
- generating a modulated digital sample sequence using a digital data modulator of the integrated circuit based on the test sequence;
- buffering a representation of the sample sequence on the integrated circuit;
- and
- comparing the buffered representation to a reference sequence.
An integrated circuit comprising:
- an input buffer to store a digital test sequence;
- a digital processor coupled to the input buffer that generates a digital output sequence;
- a test buffer coupled to the modulator to receive the output sequence, to perform an operation to reduce the size of the output sequence, and to store the reduced output sequence;
- and
- a test buffer output to enable the test buffer contents to be compared to a reference sequence.
A method comprising:
- storing a digital test sequence;
- generating a digital output sequence based on the stored test sequence using a digital processor;
- performing an operation to reduce the size of the output sequence;
- storing the reduced output sequence;
- and
- comparing the reduced output sequence to a reference sequence.
The method of claim 46, further comprising generating a digital test sequence before storing the digital test sequence.
A machine-readable medium having stored thereon data representing instructions which, when executed by a machine, cause the machine to perform operations comprising:
- storing a digital test sequence;
- generating a digital output sequence based on the stored test sequence using a digital processor;
- performing an operation to reduce the size of the output sequence;
- storing the reduced output sequence;
- and
- comparing the reduced output sequence to a reference sequence.
An interchangeable computer adapter card comprising:
- a master control unit to control operations performed on the card;
- a radio section to transmit and receive radio signals to and from the card;
- a card interface to communicate data between the card and a computer host;
- an input buffer to store a digital test sequence to be transmitted;
- a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence;
- a test buffer coupled to the modulator to receive and store a representation of the sample sequence;
- and
- a test buffer output to enable the test buffer contents to be compared to a reference sequence.
Dependencies are inferred from the claim text.