# US 2004/0187049 A1 · Very small pin count IC tester

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- Number: US 2004/0187049 A1
- Document ID: US20040187049A1
- Status: Published application
- Kind: A1
- Application number: 10/376,025
- Filed: 2003-02-27
- Published: 2004-09-23
- Earliest claimed: 2003-02-27
- Assignees: NPTest, LLC
- Inventors: Burnell G. West
- Web page: https://patentgrep.com/patent/US20040187049A1

## CPC

- G01R 31/31928: {Formatter (driver, receiver details G01R31/31924)}
- G01R 31/31922: {Timing generation or clock distribution (G01R31/3191 takes precedence)}
- G01R 31/31924: {Voltage or current aspects, e.g. driver, receiver}
- G01R 31/31926: {Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The present invention provides a method and system for testing a semiconductor device under test (DUT), such as an IC, with the help of a tester. A clock generator in the tester generates a clock signal that is sent over to the DUT on a clock signal line. Prior to an actual test, transmission and reception of data between the tester and the DUT, is synchronized with the clock signals. The invention utilizes simultaneous bi-directional signaling (SBS) for simultaneously transmitting and receiving test related data between the tester and the DUT over a single transmission line. The DUT replies with response signals corresponding to these test related data over the same transmission line. The use of SBS reduces the time required for the test, the number of pins and hence, overall cost and complexity of the testing process involved with the test.

## Claims

### Claim 1

A tester device for testing a semiconductor device, the semiconductor device comprising a first transceiver for sending and receiving test related data, the tester device comprising:
a. a clock generator to generate clock signals, the clock signals being sent by the tester device to the semiconductor device;
b. a circuit to produce test related data; and
c. a second transceiver capable of simultaneously transmitting and receiving test related data, the transmission and reception of test related data being synchronized with the clock signals.

### Claim 2 (depends on 1)

The tester device as recited in claim 1 wherein the semiconductor device is an integrated circuit.

### Claim 3 (depends on 1)

The tester device as recited in claim 1 wherein the test related data comprises:
a. a plurality of test data packets comprising:
i. a stream of test data words;
ii. a test data word count; and
iii. a cyclic redundancy check (CRC) data, the CRC data being capable of detecting errors in the transmission of the test data packet.

### Claim 4 (depends on 1)

The tester device as recited in claim 1 wherein the second transceiver comprises:
a. means for transmitting a signal to the semiconductor device;
b. means for receiving a signal at the tester device that has been transmitted by the semiconductor device;
c. means for retransmitting a packet in case there is an error in previous transmission; and
d. means for determining whether the packet received by the tester device has been received correctly.

### Claim 5 (depends on 4)

The tester device as recited in claim 4 wherein the means for receiving comprises:
a. means for separating the signal to be driven by the tester device, from the signal received by the tester device; and
b. means for comparing the received signal at the tester device with a predefined reference voltage.

### Claim 6 (depends on 4)

The tester device as recited in claim 4 wherein the means for determining comprises:
a. means for maintaining the CRC word; and
b. means for collecting the CRC word.

### Claim 7 (depends on 4)

The tester device as recited in claim 4 wherein the means for receiving a signal further comprises:
a. means for imposing a delay in a response signal, the response signal being transmitted by the semiconductor device; and
b. means for strobing the response signal when the response signal is stable.

### Claim 8 (depends on 7)

The tester device as recited in claim 7 wherein the means for imposing a delay comprises a series of buffers.

### Claim 9

A system for testing a semiconductor device with the help of a tester device, the system comprising:
a. a first circuit in the tester device to produce test related data;
b. a clock generator in the tester device to generate clock signals;
c. a first transmission line between the tester device and the semiconductor device, the first transmission line capable of carrying clock signals from the tester device to the semiconductor device, the clock signals being generated by the clock generator;
d. a second transmission line between the tester device and the semiconductor device, the second transmission line capable of carrying test related data between the tester device and the semiconductor device;
e. a first transceiver in the tester device capable of simultaneously transmitting and receiving test related data over the second transmission line, the transmission and reception of test related data being synchronized with the clock signals; and
f. a second transceiver in the semiconductor device, the second transceiver capable of simultaneously transmitting and receiving test related data over the second transmission line, the transmission and reception of test related data being synchronized with the clock signals.

### Claim 10 (depends on 9)

The system as recited in claim 9 wherein the semiconductor device is an integrated circuit.

### Claim 11 (depends on 9)

The system as recited in claim 9 wherein the first transmission line is shared among a plurality of semiconductor devices being tested by the tester device.

### Claim 12

A method for testing a semiconductor device with the help of a tester device, the semiconductor device comprising a first transceiver for sending and receiving test related data, the tester device comprising a second transceiver, a test circuit and a clock generator, the method comprising the steps of:
a. connecting a first transmission line between the tester device and the semiconductor device, the first transmission line capable of carrying clock signals from the tester device to the semiconductor device, the clock signals being generated by the clock generator;
b. connecting a second transmission line between the tester device and the semiconductor device, the second transmission line capable of carrying test related data between the tester device and the semiconductor device;
c. synchronizing transmission and reception of test related data by the tester device with the clock signals generated by the clock generator; and
d. simultaneously sending and receiving test related data over the second transmission line between the tester device and the semiconductor device, the transmission and reception of test related data being synchronized with the clock signals.

### Claim 13 (depends on 12)

The method as recited in claim 12 wherein the semiconductor device is an integrated circuit.

### Claim 14 (depends on 12)

The method as recited in claim 12 wherein the step of simultaneously sending and receiving is implemented with the help of Simultaneous Bidirectional Signaling (SBS) technique.

### Claim 15 (depends on 12)

The method as recited in claim 12 wherein the step of synchronizing transmission comprises the steps of:
a. verifying whether proper voltage levels are received and transmitted over the second transmission line;
b. transmitting clock signals continuously over the first transmission line by the clock generator; and
c. providing a timing alignment pattern to the tester device, the timing alignment pattern helping the tester device to determine the most reliable location to check for signals coming from the semiconductor device.

### Claim 16 (depends on 15)

The method as recited in claim 15 wherein the step of verifying whether proper voltage levels are received, comprises the steps of:
a. verifying continuity to pins of the semiconductor device connected to the first transmission line and the second transmission line;
b. applying power to the semiconductor device;
c. driving the second transmission line HIGH by the tester device for a predetermined number of clock cycles; and
d. driving the second transmission line LOW by the tester device for a predetermined number of clock cycles.

### Claim 17 (depends on 15)

The method as recited in claim 15 wherein the step of providing a timing alignment pattern comprises the step of driving the second transmission line in checkerboard by the semiconductor device for a predetermined number of clock cycles.

### Claim 18 (depends on 12)

The method as recited in claim 12 wherein the step of simultaneously sending and receiving test related data comprises the steps of:
a. forming of a test data packet by the tester device;
b. the tester device sending the test data packet to the semiconductor device over the second transmission line;
c. the tester device receiving a response data from the semiconductor device over the second transmission line; and
d. repeating steps a-c for all test data packets to be used in the testing method.

### Claim 19 (depends on 18)

The method as recited in claim 18 wherein the step of receiving a response data comprises the step of:
a. receiving an acknowledgement packet signifying whether the test data packet has been received correctly at the end of semiconductor device; and
b. receiving an output packet, the output packet being used to evaluate the performance of the semiconductor device.

### Claim 20 (depends on 18)

The method as recited in claim 18 wherein the step of receiving the response data at the tester device further comprises the steps of:
a. delaying the response data obtained from the second transmission line until the response data is stable with respect to the clock signals; and
b. strobing the signal carrying response data when the response data is stable.

### Claim 21 (depends on 20)

The method as recited in claim 20 wherein the step of delaying the response data at the tester device comprises the steps of:
a. adding a series of buffers to the second transmission line before the signal carrying response data is received;
b. checking the output of each buffer to determine which buffers are having stable outputs at an edge of the clock signal;
c. identifying four successive buffers having identical stable output; and
d. registering outputs of central two of the four successive buffers in two D-type flip-flops.

### Claim 22 (depends on 18)

The method as recited in claim 18 wherein the step of sending the test data packet to the semiconductor device comprises the steps of:
a. maintaining a CRC register;
b. sending the test data packet one data word at a time;
c. keeping a count of the test data words sent; and
d. sending contents of the CRC register, if all the test data words have been sent.