US 2004/0186871 A1Published application

Multiplier circuit

OwnerDonato Ettorre, Bruno Melis +1inventors

InventorsDonato Ettorre, Bruno Melis, Alfredo Ruscitto

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Abstract

An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Zn, Jn) into a first part (msb(Zn), msb(Jn)) that is the power of 2 immediately lower or equal to the input signal and a second part (Zn—msb(Zn), Jn—msb(Jn)) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X,Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X,Y) is calculated.

Claims10

Dependent claims

Multiplier circuit (10) for generating, starting from at least a first (X) and a second (Y) binary digital signal representative of respective factors to be multiplied each other, an output signal (X-Y) representative of the product of said factors, characterised in that it comprises:

at least one extracting powers of 2 module (15 through 18) able to subdivide a respective input signal (Zn, Jn) into a first part (msb(Zn), msb(Jn)) that is the power of 2 immediately lower or equal to said respective input signal (Zn, Jn) and a second part (Zn−msb(Zn), Jn−msb(Jn)) corresponding to the difference between said respective input signal and said first part,
an input module (13, 14) for applying at least one (X or Y) of said first and second binary digital signal as said respective input signal to said at least one extracting module (15 through 18), and
a shifter module (19) co-operating with said at least one extracting module (15 through 18) for generating at least one first portion of said output signal (X·Y) by means of a shift operation performed on the other (Y or X) between said first and second binary digital signal by a number of positions identified by the first part of said one between said first (X) and second (Y) binary digital signal generated by said extracting module (15 through 18).

Method for generating, starting from at least a first (X) and a second (Y) binary digital signal representative of respective factors to be multiplied each other, an output signal (X·Y) representative of the product of said factors, characterised by the steps of:

extracting (15 through 18) from said at least first or second binary digital signal representative of a respective input signal (Zn, Jn) a first part (msb(Zn), msb(Jn)) that is the power of 2 immediately lower or equal to said respective input signal (Zn, Jn) and a second part (Zn−msb(Zn), Jn−msb(Jn)) corresponding to the difference between said respective input signal and said first part, and
generating at least a first portion of said output signal (X·Y) by means of a shift operation performed on the other (Y or X) between said first and second binary digital signal by a number of positions identified by the first part of said one between said first (X) and second (Y) binary digital signal.

Dependencies are inferred from the claim text.