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US 2004/0177332 A1Published application
Method and system for logic equivalence checking
AssigneeCadence Design Systems, Inc.
InventorsManish Pandey, Yung-Te Lai, Bret Siarkowski, Kei-Yong Khoo, Chih-Chang Lin
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Abstract
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
Claims70
A method of circuit equivalence checking, comprising:
- solving at least a first equivalence checking problem;
- storing at least a first solution to at least the first equivalence checking problem;
- and
- reusing at least part of the first solution to the first equivalence checking problem for a second equivalence checking problem.
1 more element
An apparatus for circuit equivalence checking, comprising:
- one or more persistent caches including:
- one or more cached objects including:
- one or more problem signatures;
- and
- one or more algorithm traces;
- and
- one or more cache managers accepting one or more equivalence checking queries and returning at least part of at least one cached object from the one or more persistent caches at least partly in response to the one or more equivalence checking queries.
4 more elements
Dependencies are inferred from the claim text.