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AssigneeSun Microsystems, Inc.
InventorsAveek Sarkar, Shyam Sundar, Peter F. Lai, Rambabu Pyapali
Estimating the term…
The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time- domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.
A method in use for in a design of an integrated circuit, the method comprising:
A circuit analysis tool that prepares a time-domain staggered distribution of modeled switching for signal regeneration devices in nets of the integrated circuit design prior to preparing a layout of the integrated circuit design and aggregates power consumption of selected groups of the signal generation devices for use in revision of the integrated circuit design.
A semiconductor integrated circuit comprising:
An apparatus comprising:
A computer readable encoding of a semiconductor integrated circuit design, the computer readable encoding comprising:
Dependencies are inferred from the claim text.