Digital system and a method for error detection thereof

A digital system (1) for processing a digital input vector (p_InV), comprising p bits (I1, I2, . . . , Ip), for providing a digital output vector (q_OutV) comprising q bits (O1, O2, . . . , Oq), the digital system (1) comprising

• a first input terminal (101) for receiving p_InV,
• a first output terminal (102) for transmitting q_OutV,
• a digital processing unit (100) coupled to the first input terminal (101) for processing the p_InV for generating the digital output vector by means of a targeted digital transfer function (TDTF), the digital processing unit (100) comprising a Module under Test (110) having a second input terminal (105) coupled to the first input terminal (101) and a second output terminal (103) for generating a digital vector (T) having r bits (T1, T2, . . . , Tr), in response to the digital input vector p_InV.
• an Actual Parity Generator (200) having a third input terminal coupled to the second output terminal (103) and conceived for providing at a third output terminal (201) an output signal (AP) representing the parity of the vector T,
• a comparator (400) having a fourth input terminal coupled to the third output terminal (201) and a fifth input terminal coupled to a sixth output terminal (301) realizing a digital comparison between the signal AP and another parity signal (CP) and providing an output signal (ED) at a seventh output terminal (401) indicating whether or not the signal (AP) equals the signal (CP), characterized in that the digital system (1) further comprises a State Parity Generator (SPG) (300) having a sixth input terminal (106) coupled to the input terminal (101) and the sixth output terminal (301) coupled to the fifth input terminal, the SPG generating the other parity signal (CP) of an equivalent with respect to parity of the module (110), the other parity signal (CP) being generated from the digital input vector p_InV.