Familial correction with non-familial double bit error detection

Apparatus for detecting and correcting all 15 possible familial bit errors in data from any single 4-bit RAM in a first data word of 128 bits and for also detecting all double bit, non-familial errors and for detecting uncorrectable multi-bit errors in said first 128 bit word, wherein said first 128 bit word is a data word storable in a RAM memory within a computer system which generates 16 check bits (FIG. 5, 54) from said 128 bit data word (53) when sending said 128 bit data word to said RAM memory, and wherein both said 128 bit data word and said 16 bit check bit data are retrievable together therefrom, and wherein said computer system has input circuits to said memory for sending said first data word to said RAM memory and output circuits for retrieving from storage a retrieved 128 bit data word from said RAM memory, wherein said retrieved 128 bit data word will be equivalent to said first data word if no errors occur, said apparatus comprising:

• a syndrome generator (FIG. 6, 60A, 60B) for generating 16 syndrome bits from said 16 check bits and said 128 bit data word retrieved from said RAM memory, a syndrome decode (81) and comparator (82) circuit for producing a no error signal, a correctable data signal, and a correctable check bit signal, wherein said correctable data signal is produced by determining if a correction was required by decoding said 16 bit syndrome through a syndrome decode circuit, said correctable check bit signal is produced by determining if a correction is required for said generated 16 check bits, and wherein said no error signal is produced if said syndrome signal value is a predetermined value.

Apparatus for detecting and correcting all 15 possible familial bit errors in data from any single 4-bit RAM in a first data word of 128 bits and for also detecting all double bit, non-familial errors and for detecting uncorrectable multi-bit errors in said first 128 bit word, wherein said first 128 bit word is a data word storable in a RAM memory within a computer system which generates 16 check bits from said 128 bit data word when sending said 128 bit data word to said RAM memory, and wherein both said 128 bit data word and said 16 bit check bit data are retrievable together therefrom, and wherein said computer system has input circuits to said memory for sending said first data word to said RAM memory and output circuits for retrieving from storage a retrieved 128 bit data word from said RAM memory, wherein said 11 retrieved 128 bit data word will be equivalent to said first data word if no errors occur, said apparatus comprising:

• a check bit regenerator associated with said output circuits for generating in said predetermined manner, a regenerated 16 check bits from said retrieved 128 bit data word,
• a syndrome generator for generating 16 syndrome bits from said regenerated 16 check bits wherein each of said regenerated 16 check bits is modula2 added to a one of said generated check bits, producing thereby a 16 bit syndrome,
• a syndrome decode and comparator circuit for producing a no error signal, a correctable data signal, and a correctable check bit signal, wherein said correctable data signal is produced by determining if a correction was required by decoding said 16 bit syndrome through a syndrome decode circuit, said correctable check bit signal is produced by determining if a correction is required for said generated 16 check bits, and wherein said no error signal is produced if said syndrome signal value is a predetermined value.

Method for detecting and correcting all 15 possible familial bit errors in data from any single 4-bit RAM family in a first data word of 128 bits and for also detecting all double bit, non-familial errors and for detecting uncorrectable multi-bit errors in said first 128 bit word, wherein said first 128 bit word is a data word storable into in a RAM memory within a computer system and retrievable therefrom, and wherein said computer system for performing said method has input circuits to said memory for sending said first data word to said RAM memory and output circuits for retrieving from storage a retrieved 128 bit data word from said RAM memory, wherein said retrieved 128 bit data word will be equivalent to said first data word if no errors occur, said method comprising:

• a) providing a 16 bit check bit output for said first data word at any time said first data word is to be stored in said RAM memory, and storing said provided 16 bit check bit output with said first data word,
• b) retrieving said first data word along with said stored 16 bit check bit output,
• c) producing a 16 bit syndrome from said stored 16 bit check bit output,
• d) determining if said 16 bit syndrome is a predetermined value and if it is said predetermined value, generating a “no error” signal,
• e) decoding said 16 bit syndrome to indicate which, if any, of said 128 bits of said retrieved first data word are in correctable error and, if any are in correctable error, producing a “correctable error” signal and a signal indicating which of said 128 bits of said retrieved first data word are in correctable error,
• f) correcting any correctable error, and
• g) producing an “uncorrectable error” signal if either (i) said correctable error signal and said no error signal do not agree, or (ii) said correctable ECC error signal and said no error signal do not agree, otherwise, producing a “good data” signal.