Fast bit-parallel viterbi decoder add-compare-select circuit
AssigneeIntel Corporation
InventorsSanu K. Mathew, Ram Krishnamurthy, Hoang Q. Dao
Life of this patent
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Abstract
A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
Claims28
A decoding circuit, comprising:
- a first adder having a first state input, a first branch input, and a first adder output, the first adder adding the first state input and the first branch input to generate the first adder output;
- a second adder having a second state input, a second branch input, and a second adder output, the second adder adding the second state input and the second branch input to generate the second adder output;
- a comparator having a first adder input, a second adder input, and a comparator output, the comparator comparing the first adder input and the second adder input to generate the comparator output;
- a multiplexer having a first multiplexer input, a second multiplexer input, a select input, and a multiplexer output, the multiplexer selecting one of the first multiplexer input and the second multiplexer input based on the select input to generate the multiplexer output;
- a storage unit coupled to the multiplexer output, the storage unit storing the multiplexer output;
- and
- an inverter coupled between the second adder output and the second multiplexer input, the inverter inverting the second adder output.
A add-compare-select circuit, comprising:
- an adder having a plurality of inputs and a plurality of outputs, the adder adapted to add the plurality of inputs at an operating frequency;
- a comparator coupled to the adder, the comparator adapted to compare the plurality of outputs at the operating frequency;
- and
- a selector coupled to the comparator and the adder, the selector adapted to select at least one of the plurality of outputs at the operating frequency;
- wherein the operating frequency approximately equals a symbol rate.
A method for data detection, comprising:
- receiving data at a data rate;
- adding a first branch metric and a first state metric at the data rate;
- adding a second branch metric and a second state metric at the data rate;
- generating a first output signal based on the addition of the first branch metric and the first state metric at the data rate;
- generating a second output signal based on the addition of the second branch metric and the second state metric at the data rate;
- comparing the first output signal and the second output signal at the data rate;
- generating a select signal based on the comparison of the first output signal and the second output signal at the data rate;
- and
- selecting one of the first output signal and the second output signal based on the select signal.
A system comprising:
- a die comprising a microprocessor;
- and
- an off-die component in communication with the microprocessor;
- wherein the microprocessor comprises:
- an add-compare-select circuit, comprising:
- an adder having a plurality of inputs and a plurality of outputs, the adder adapted to add the plurality of inputs at an operating frequency and;
- a comparator coupled to the adder component, the comparator adapted to compare the plurality of outputs at the operating frequency;
- and
- a selector coupled to the comparator and the adder, the selector adapted to select at least one of the plurality of outputs at the operating frequency;
- wherein the operating frequency approximately equals a symbol rate.
Dependencies are inferred from the claim text.