Scalable scan-path test point insertion technique

A logic circuit comprising at least one input, one output and a delay fault circuit, said delay fault circuit including:

• a first standard scan cell;
• a test point positioned immediately after the first standard scan cell in a scan chain;
• and
• a second standard cell positioned immediately after the test point in the scan chain,
• where the test point is positioned to prevent shift dependency identified to occur between the first and second standard scan cells in the delay fault circuit.

A method of testing a logic circuit comprising:

• loading a first test pattern into a first standard scan cell in a scan chain;
• loading an output of the first standard cell into a combinational test point in the scan chain;
• and
• loading an output of the combinational test point into a second standard scan cell in the scan chain.

An integrated circuit comprising at least one logic circuit and at least one delay fault circuit, the delay fault circuit including:

• a first standard scan cell in a scan chain;
• a combinational test point positioned immediately after the first standard scan cell in the scan chain;
• and
• a second standard scan cell positioned immediately after the combinational test point in the scan chain.

A method of testing a circuit comprising:

• a) applying a first set of two pattern tests using a skewed-load approach under standard scan environments;
• b) applying a second set of two pattern tests that target faults that are not detected in step a using a broadside-load approach under standard scan environments;
• and
• c) dividing test efforts required for remaining faults into a plurality of sub-phases and under each sub-phase enabling a different set of test points in every activation and propagation test cycle while the test points other than said different set of test points remain disabled.

A method for designing test points for testing a circuit and identifying test points that should be enabled during each sub-phase of the testing, comprising:

• a) identifying dependency untestable transition delay faults;
• b) initializing global variables;
• c) initializing a current test cube pair set and a current test point vector;
• d) stopping the procedure if no more untested fault exists in a fault list;
• e) selecting and marking an unmarked fault that has a minimum test generation cost in the fault list;
• f) generating a test cube pair for the unmarked fault;
• g) if the test cube pair generated in step f cannot be added to the current test cube pair set due to a conflict with any other test cube pair in the current test cube pair set, discarding the generated test cube pair and going to step e;
• h) adding the generated test cube pair into the current test cube pair set and updating the current test point vector accordingly;
• and
• i) if no more test cube pair can be added into the test cube pair set without conflict with other test cube pairs in the current test cube pair set, updating a global test point vector and going to step c.