Structure and method for detecting errors in a multilevel memory device with improved programming granularity
OwnerAngelo Viscontiinventor
Life of this patent
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Abstract
An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.
Claims23
An error detection structure for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells,
- characterized in that
- the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.
The structure according to any claim from 1 to 3, further including means for storing an indicator of change of at least one digit of the second subset and means for selectively disabling the means for detecting errors according to the indicator of change.
The structure according to any claim from 1 to 4, wherein the digits of the block are organized into a plurality of words partitioned into a first and a second set, each word being suitable to be individually processed in the memory device, and wherein the structure further includes means for associating the words of the first set and the words of the second set with the digits of the first subset and the digits of the second subset of the block, respectively.
A multilevel memory device including a plurality of memory cells and the error detection structure according to any claim from 1 to 7.
An error detection method for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, the method including the steps of:
- detecting errors in the values of a selected block of memory cells,
- characterized by the step of
- partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the step of detecting errors only operating on the digits of the second subset of the block.
An error detection circuit for a multilevel memory device including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits, the circuit comprising:
- an encoding circuit coupled to the memory cells and adapted to receive a page of bits including a plurality of data words, the encoding circuit operable to arrange the bits of the data words for storage in the memory cells and to develop error checkbits for some of the words, and operable to store the arranged bits and the error check bits in the memory cells;
- and
- a decoding circuit coupled to the memory cells and operable to read the arranged bits of the data words and the error check bits from the memory cells, the decoding circuit providing selected ones of the data words as read from the memory cells and performing error checking correction on the other ones of the data words using the bits of those other words and the check bits read from the memory cells, and providing the other words after peforming error checking and correction on those other words.
A memory device, comprising:
- a memory cell array including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits;
- an encoding circuit coupled to the memory cells and adapted to receive a page of bits including a plurality of data words, the encoding circuit operable to arrange the bits of the data words for storage in the memory cells and to develop error checkbits for some of the words, and operable to store the arranged bits and the error check bits in the memory cells;
- and
- a decoding circuit coupled to the memory cells and operable to read the arranged bits of the data words and the error check bits from the memory cells, the decoding circuit providing selected ones of the data words as read from the memory cells and performing error checking correction on the other ones of the data words using the bits of those other words and the check bits read from the memory cells, and providing the other words after peforming error checking and correction on those other words.
An electronic system including a memory, the memory comprising:
- a memory cell array including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits;
- an encoding circuit coupled to the memory cells and adapted to receive a page of bits including a plurality of data words, the encoding circuit operable to arrange the bits of the data words for storage in the memory cells and to develop error checkbits for some of the words, and operable to store the arranged bits and the error check bits in the memory cells;
- and
- a decoding circuit coupled to the memory cells and operable to read the arranged bits of the data words and the error check bits from the memory cells, the decoding circuit providing selected ones of the data words as read from the memory cells and performing error checking correction on the other ones of the data words using the bits of those other words and the check bits read from the memory cells, and providing the other words after peforming error checking and correction on those other words.
A method for the detection and correction of errors in data bits stored in a multilevel memory device including a plurality of memory cells, each memory cell being programmable at more than two levels and each level representing a logic value consisting of a plurality of bits, the method comprising:
- encoding a received data word including a plurality of sub data words, each sub data word including a plurality of bits, the encoding including,
- arranging the bits of the sub data words;
- developing error check bits for some of the sub data words;
- storing the arranged bits and error check bits in the memory cells;
- and
- decoding the data word stored in the memory cells by,
- reading the arranged and error check bits from the memory cells;
- providing selected ones of the data words as read from the memory cells;
- performing error checking and correction on the other ones of the data words using the bits of those other words and the check bits read from the memory cells;
- and
- providing the other words after peforming error checking and correction on those other words.
Dependencies are inferred from the claim text.