Frequency detection circuit and data processing apparatus

A frequency detection circuit for detecting frequency abnormality of a check target clock, comprising:

• a status holding register for storing rise information showing a rise and fall information showing a fall of the check target clock and outputting an error detection signal showing the frequency abnormality when the fall information is not stored within a predetermined time from the rise of the check target clock or the rise information is not stored within a predetermined time from the fall of the check target clock,
• a rise/fall detection circuit for detecting a rise and a fall of the check target clock and outputting a rise detection signal in response to said rise and a fall detection signal in response to said fall, and
• an edge detection signal generation circuit for generating the rise information and the fall information with reference to the rise detection signal and the fall detection signal and outputting an edge detection signal including these information to the status holding register.

A data processing apparatus comprising:

• a reference clock generation circuit for outputting a reference clock,
• a frequency detection circuit for inputting a check target clock supplied from an outside and the reference clock and outputting an error detection signal when a time width of a half cycle of the check target clock is longer than a predetermined time,
• a signal processing circuit being reset in the case of receiving the error detection signal outputted from the frequency detection circuit.