Apparatus and method for capturing the program counter address associated with a trigger signal in a target processor
OwnerGary L. Swobodainventor
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Abstract
In a target processor, trigger signals that result in changes in the program execution must be identified and communicated to a host processing unit. The target processor uses the generation of a trigger signal by preselected events to store the indicia of the preselected events in a register for transfer to the host processing unit. The program counter contents related to the trigger signal is delayed to accommodate the target processor delay and stored when a trigger signals is generated.
Claims14
In a target processor, apparatus for storing a program counter address related to the generation of the a trigger signal, the apparatus comprising:
- a trigger generation unit coupled to the plurality of event signal generation units, the trigger generation unit responsive to at least one preselected event signal for generating an associated trigger signal, the trigger generating unit also generating a trigger control signal;
- a register, the register having program counter address related to the trigger signal applied thereto, the register storing the program counter address in response to a control signal generated by the trigger generation unit when the trigger signal is generated;
- and
- a delay unit, the delay unit delaying application of the program counter address to the register.
The method of storing a program counter address related to the generation of a trigger signal, the method comprising:
- generating a event signal for each predetermined event;
- applying each event signal to a trigger generation unit;
- when a predetermined event signal or combination of event signals is applied to the trigger generation unit, the trigger generation unit providing a trigger signal and a trigger control signal;
- and
- applying the trigger control signal to the storage unit, the storage unit storing the program counter address resulting in the generation of the trigger signal in the storage unit in response to the trigger control signal.
A target processor comprising:
- a state machine, the state machine generating a first event signal in response to a configuration of the target processor;
- at least one event detection unit, each event detection unit responsive to predetermined configuration of the target processing unit for generating a related event signal;
- a trigger generation unit, the trigger generation unit generating trigger signal in response to at least one of the first and the related event signals, the trigger unit generating a trigger control signal when the a trigger signal is generated;
- and
- a storage unit, the storage unit coupled to the program counter, the program counter applying address signals to the storage unit, the storage unit storing a program counter address in response to the trigger control signal.
Dependencies are inferred from the claim text.