Processor having a RAT state history recovery mechanism

An apparatus for allowing a processor to recover from a failure of a predicted path of instructions comprising:

• a plurality of physical registers;
• a primary array storing a first speculative state of the processor including a mapping from logical registers to physical registers,
• a secondary array coupled to the primary array, the secondary array storing a second speculative state including a mapping from logical registers to physical registers, the second speculative state being behind or earlier than the primary speculative state;
• and
• a history buffer coupled to the secondary array and storing historical physical register to logical register mappings performed for each of a plurality of instructions.

An apparatus for allowing a processor to recover from a failure of a predicted path of instructions comprising:

• a plurality of physical registers;
• a primary array storing a mapping from logical registers to physical registers, the primary array storing a current speculative state of the processor;
• an allocator allocating an available physical register as the physical destination for storing the execution results of an instruction, the allocated physical register corresponding to a logical register;
• a history buffer coupled to the secondary array and storing historical physical register to logical register mappings performed for each of a plurality of instructions of a predicted path;
• a secondary array coupled to the primary array and the history buffer, the secondary array storing a secondary speculative state of the processor including a mapping from logical registers to physical registers, the secondary array being movable to any instruction between the point of physical register allocation and retirement based on the history buffer, the secondary array being movable to any location or instruction independent of which instructions have been executed;
• wherein the secondary array can be copied to the primary array to allow the processor to recover from the failure in the predicted path.

A method of recovering from a failure in a predicted path in a processor, the processor including a plurality of physical registers and a plurality of logical registers, the method comprising:

• receiving an instruction;
• allocating an available physical register as the physical destination for the instruction, the allocated physical register corresponding to a logical register;
• storing in a primary array a current mapping between the logical register and the currently allocated physical register;
• storing in a history buffer the logical register, the new allocated physical register corresponding to the logical register, and an old physical register previously corresponding to the logical register;
• moving, based on the register mappings stored in the history buffer, a secondary array to a location in the predicted path of instructions where a failure may occur;
• detecting whether a path failure occurs near the location of the secondary array;
• copying the secondary array to the primary array if a predicted path failure occurs near the location of the secondary array to allow the primary array of the processor to recover from the path failure to a correct state.

A method of a register alias table recovering from a failure in a predicted path in a processor, the processor including a plurality of physical registers and a plurality of logical registers, the method comprising:

• using a primary array to store a current speculative state of logical register to physical register mappings;
• using a history buffer to store old and new register mappings that allow each of several instructions in a predicted path to be performed or reversed;
• using a secondary array to store a secondary speculative state of logical register to physical register mappings at a location in the predicted path where a path failure may occur;
• and
• copying the secondary array to the primary array if a path failure occurs at or near the location where the secondary array is located.