Microprocessor
AssigneeFujitsu Limited
InventorKoutarou Tagawa
Life of this patent
Estimating the term…
Abstract
A microprocessor which can shorten a testing period and facilitate the production of a test program is provided. The microprocessor of the present invention includes a CPU which performs certain arithmetic operations, an address bus connected to the CPU, a circuit unit, such as comparators, which utilizes an address on the address bus. In an function test of the circuit unit, a test circuit, instead of the CPU, generates a test address for testing the circuit unit through the address bus. Also, a special instruction is issued to transmit an address through the bus so as to prevent the CPU from overrunning
Claims7
A microprocessor comprising:
- a CPU which performs certain arithmetic operations;
- an address bus connected to the CPU;
- a circuit unit which utilizes an address on the address bus;
- and
- a test circuit which generates a test address for testing the circuit unit.
A microprocessor comprising:
- a CPU which performs certain arithmetic operations;
- an instruction bus which is connected to the CPU and includes an instruction address bus and an instruction data bus;
- a circuit unit which can be tested with the use of an address on the instruction address bus;
- and
- a test circuit which inputs a return instruction into the CPU via the instruction data bus when receiving a branch instruction from the CPU in an initial state immediately after actuation.
A microprocessor comprising:
- a program for fetching an instruction at a predetermined address, and executing an instruction to carry out an unconditional return without using a code at a branch destination as an instruction after a branch occurs to a designated address.
A microprocessor comprising:
- a CPU having an instruction bus and a data bus which are independent of each other,
- wherein
- an instruction to make data read access to the instruction bus is issued.
Dependencies are inferred from the claim text.