US 2004/0177231 A1 · Data processor

Abstract

A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Claims20

Dependent claims

A data processor formed on an LSI chip comprising:

an instruction address generator generating an instruction address;
an instruction cache memory having entries each storing an instruction corresponding to the instruction address;
an instruction decoder decoding an instruction read out from said cache memory;
an operand address generator generating an operand address in response to an output signal of said instruction decoder;
and
an operand cache memory having entries each storing operand data corresponding to the operand address in its entry,
wherein the data processor executes a first instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective,
wherein the first instruction is stored in a main memory with other instructions, the main memory being external to the data processor,
wherein the instruction address generator generates the instruction address as a logic address, and
wherein an address of the main memory is a physical address.

7 more elements

A data processor formed on an LSI chip comprising:

an instruction address generator;
an instruction cache memory;
an instruction decoder;
an operand address generator;
and;;
an operand cache memory,
wherein the instruction address generator generates an instruction address,
wherein said instruction cache memory has entries each storing an instruction corresponding to the instruction address in its entry,
wherein into said instruction decoder is input an instruction from said instruction cache memory and said decoder outputs a decoded result,
wherein said operand address generator generates an operand address response to the decoded result of said instruction decoder,
wherein said operand cache memory has entries each storing operand data corresponding to the operand address in its entry,
wherein when the data processor executes a first instruction, the data processor invalidates the instruction and operand cache memories,
wherein the first instruction is stored in a main memory with other instructions, the main memory being external to the data processor,
wherein the instruction address generator generates the instruction address as a logic address, and
wherein an address of the main memory is a physical address.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/796,958Filed 11 Mar 2004

Priority

JP 60-5051215 Mar 1985

Published

9 Sep 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/30047
To perform operations on memory: prefetch instructions; cache control instructions
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/3802
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching
G06F 9/3824
Concurrent instruction execution, e.g. pipeline or look ahead: operand accessing

Family

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