Microcomputer application system, microcomputer, signal processing system and signal processing LSI
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTokuyuki Saijo, Kouji Kitamura
Life of this patent
Estimating the term…
Abstract
An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM1 stored in the external ROM to a high-speed processing region of an internal RAM. When a fetch address AZ1 specified by the MPU indicates a region of the external ROM in which the high-speed processing part PGM1 is stored, the address translation unit translates the fetch address AZ1 to the address AF of a region of the internal RAM corresponding to the high-speed processing part PGM1.
Claims22
A microcomputer application system comprising:
- a microcomputer including an MPU, an internal RAM, and a bus for connecting the MPU and the internal RAM;
- an external ROM connected to the bus;
- first means for transferring a high-speed processing part which is part of a program stored in the external ROM and is required to be operated at high speed from the external ROM to the internal RAM;
- and
- second means for translating, when a fetch address which the MPU specifies to fetch program data indicates a region of the external ROM in which the high-speed processing part is stored, the fetch address to an address of a region of the internal RAM corresponding to the high-speed processing part.
A microcomputer which includes an MPU, an internal RAM, and a bus for connecting the MPU and the internal RAM and is so configured that an external ROM is connectable to the bus, the microcomputer comprising;
- first means for transferring a high-speed processing part which is part of a program stored in the external ROM and is required to be operated at high speed from the external ROM to the internal RAM, and
- second means for translating, when a fetch address which the MPU specifies to fetch program data indicates a region of the external ROM in which the high-speed processing part is stored, the fetch address to an address of a region of the internal RAM corresponding to the high-speed processing part.
A microcomputer which includes an MPU, an internal RAM, and a bus for connecting the MPU and the internal RAM, the microcomputer comprising:
- a ROM which is connected to the bus and has a lower access speed by the MPU than that of the internal RAM;
- first means for transferring a high-speed processing part which is part of a program stored in the external ROM and is required to be operated at high speed from the external ROM to the internal RAM;
- and
- second means for translating, when a fetch address which the MPU specifies to fetch program data indicates a region of the external ROM in which the high-speed processing part is stored, the fetch address to an address of a region of the internal RAM corresponding to the high-speed processing part.
A microcomputer which includes an MPU and is so configured to be connectable to an external ROM and an external RAM, the microcomputer comprising:
- first means for transferring a high-speed processing part which is part of a program stored in the external ROM and is required to be operated at high speed from the external ROM to the external RAM;
- and
- second means for translating, when a fetch address which the MPU specifies to fetch program data indicates a region of the external ROM in which the high-speed processing part is stored, the fetch address to an address of a region of the external RAM corresponding to the high-speed processing part.
A microcomputer which includes an MPU and is so configured to be connectable to an external RAM, the microcomputer comprising:
- a ROM having a lower access speed by the MPU than that of the external RAM;
- first means for transferring a high-speed processing part which is part of a program stored in the ROM and is required to be operated at high speed from the ROM to the external RAM;
- and
- second means for translating, when a fetch address which the MPU specifies to fetch program data indicates a region of the ROM in which the high-speed processing part is stored, the fetch address to an address of a region of the external RAM corresponding to the high-speed processing part.
A signal processing system comprising:
- a signal processing LSI including an operation processing unit, an internal first storage unit, and a bus for connecting the operation processing unit and the first storage unit;
- an external second storage unit which is connected to the bus and has a lower access speed by the operation processing unit than that of the first storage unit;
- first means for transferring a high-speed processing part which is part of a program stored in the second storage unit and is required to be operated at high speed from the second storage unit to the first storage unit;
- and
- second means for translating, when a fetch address which the operation processing unit specifies to fetch program data indicates a region of the second storage unit in which the high-speed processing part is stored, the fetch address to an address of a region of the first storage unit corresponding to the high-speed processing part.
A signal processing LSI which includes an operation processing unit, an internal first storage unit, and a bus for connecting the operation processing unit and the first storage unit and is so configured that an external second storage unit having a lower access speed by the operation processing unit than that of the first storage unit is connectable to the bus, the LSI comprising:
- first means for transferring a high-speed processing part which is part of a program stored in the second storage unit and is required to be operated at high speed from the second storage unit to the first storage unit;
- and
- second means for translating, when a fetch address which the operation processing unit specifies to fetch program data indicates a region of the second storage unit in which the high-speed processing part is stored, the fetch address to an address of a region of the first storage unit corresponding to the high-speed processing part.
A signal processing LSI which includes an operation processing unit, an internal first storage unit, and a bus for connecting the operation processing unit and the first storage unit, the LSI comprising:
- second storage unit which is connected to the bus and has a lower access speed by the operation processing unit than that of the first storage unit;
- first means for transferring a high-speed processing part which is part of a program stored in the second storage unit and is required to be operated at high speed from the second storage unit to the first storage unit;
- and
- second means for translating, when a fetch address which the operation processing unit specifies to fetch program data indicates a region of the second storage unit in which the high-speed processing part is stored, the fetch address to an address of a region of the first storage unit corresponding to the high-speed processing part.
A signal processing LSI which includes an operation processing unit and is so configured to be connectable to an external first storage unit and an external second storage unit having a lower access speed by the operation processing unit than that of the first storage unit, the LSI comprising:
- first means for transferring a high-speed processing part which is part of a program stored in the second storage unit and is required to be operated at high speed from the second storage unit to the first storage unit;
- and
- second means for translating, when a fetch address which the operation processing unit specifies to fetch program data indicates a region of the second storage unit in which the high-speed processing part is stored, the fetch address to an address of a region of the first storage unit corresponding to the high-speed processing part.
A signal processing LSI which includes an operation processing unit and is so configured to be connectable to an external first storage unit, the LSI comprising:
- second storage unit having a lower access speed by the operation processing unit than that of the first storage unit;
- first means for transferring a high-speed processing part which is part of a program stored in the second storage unit and is required to be operated at high speed from the second storage unit to the first storage unit;
- and
- second means for translating, when a fetch address which the operation processing unit specifies to fetch program data indicates a region of the second storage unit in which the high-speed processing part is stored, the fetch address to an address of a region of the first storage unit corresponding to the high-speed processing part.
Dependencies are inferred from the claim text.