Bus architecture techniques employing busses with different complexities
AssigneeBroadcom Corporation
InventorBrian Schoner
Life of this patent
Estimating the term…
Abstract
An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity.
Claims25
In an integrated circuit system comprising a system bus with a first complexity, apparatus for enabling communication among a plurality of devices in part through the system bus comprising:
- at least a first device;
- at least a second device;
- and
- a bus interface coupled to the system bus, coupled to the first device through a first bus with a second complexity less than the first complexity and coupled to the second device through a second bus with a third complexity less than the first complexity.
In an integrated circuit system comprising plurality of devices interconnected by a first bus and one or more second busses, a method of transmitting data among the plurality of devices with reference to an address associated with the data comprising:
- operating the first bus at the first complexity;
- operating the one or more second busses at a second complexity less than the first complexity;
- translating between the first complexity and the second complexity so that the data is routed on the first bus and the one or more second busses in response to the address or is routed only on the one or more second busses in response to the address.
Dependencies are inferred from the claim text.