Bus interface with variable resistance coupling
OwnerDavid C. Campbell, Anna Yeeinventors
Life of this patent
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Abstract
An interface for coupling a device to a bus suitably includes a first resistive path having a first electrical resistance and a second resistive path having a second electrical resistance different from the first electrical resistance, with a switch configured to switchably couple the device to the bus via the first resistive path if the device operates at a first data rate, and to couple the device to the bus via the second resistive path if the device operates at a second data rate different from the first data rate. The interface may be used to provide an appropriate resistive coupling for devices that support conventional peripheral component interface (PCI) bus standards and/or PCI-X standards.
Claims16
An interface for coupling a device to a bus, the coupler comprising:
- a first resistive path having a first electrical resistance;
- a second resistive path having a second electrical resistance different from the first electrical resistance;
- and
- a switch configured to switchably couple the device to the bus via the first resistive path if the device operates at a first data rate, and to couple the device to the bus via the second resistive path if the device operates at a second data rate different from the first data rate.
A circuit for coupling a device to a bus within a computing system, the circuit comprising:
- a first resistive path between the device and the bus, the first resistive path having a first electrical resistance;
- a second resistive path between the device and the bus, the second resistive path having a second electrical resistance that is less than the first electrical resistance;
- and
- an analog switch receiving having a first input coupled to the bus, a second input configured to receive a control signal, a first output coupled to the first resistive path, and a second output coupled to the second resistive path, wherein the analog switch is operable to switchably connect the first input to either of the first output or the second output as a function of the control signal.
A computing system having a bus interconnecting a processor, a memory and an interface to an external device, the interface comprising:
- a first resistive path having a first electrical resistance;
- a second resistive path having a second electrical resistance different from the first electrical resistance;
- and
- a switch configured to switchably couple the device to the bus via the first resistive path if the device operates at a first data rate, and to couple the device to the bus via the second resistive path if the device operates at a second data rate different from the first data rate.
An interface for coupling a device to a bus within a computing host, the interface comprising:
- means for receiving the device at an interface having a high resistance path and a low resistance path;
- means for determining a data rate of the device;
- and
- means for selecting the high resistance path or the low resistance path for coupling the device to the bus as a function of the data rate of the device.
A method of coupling a device to an address bus, the method comprising the steps of:
- receiving the device at an interface having a high resistance path and a low resistance path;
- determining a data rate of the device;
- and
- coupling the device to the bus via the high resistance path or the low resistance path as a function of the data rate of the device.
Dependencies are inferred from the claim text.