Dual time sliced circular bus
AssigneeInternational Business Machines Corporation
InventorsKenneth J. Goodnow, Riyon Harding, Frances A. Kampf, Thomas M. Lepsic
Life of this patent
Estimating the term…
Abstract
A dual time sliced circular bus extending in opposite directions, and optionally interspersed so as to reduce noise. The width of the buses can either be dynamic or static depending upon the particular implementation. Circulating on each of the buses is a predetermined number of data structures for either transmitting an address operation or data. Each of the cores can use the data structures for transmitting and receiving data between themselves according to a transmitting and receiving scheme.
Claims21
An integrated circuit comprising:
- a first bus for transmitting data;
- a plurality of first data structures each of which is continuous transmitted on the first bus;
- and
- a plurality of cores each of which is coupled to the first bus to receive each one of the first data structures, and to transmit data in the first data structures.
The integrated circuit 1 further comprising:
- a second bus for transmitting data;
- and
- a plurality of second data structures each of which is continuously transmitted on the second bus.
A bus structure comprising:
- a first bus to transmit data;
- a plurality of cores each coupled to the first bus;
- and
- a plurality of first data structures to transmit data, each one of the data structures being continuously circulated on the first bus.
Dependencies are inferred from the claim text.