Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller
AssigneeSTMicroelectronics S.r.l.
InventorSaverio Pezzini
Life of this patent
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Abstract
A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.
Claims9
A method of controlling the generation of interrupt command in a microprocessor system, comprising
- associating pre-established priority values to respective possible interrupts (INT0, . . . , INTm),
- storing received interrupts (INT0, . . . , INTm), in a plurality of pending interrupt registers (INT PENDING REG) and storing the priority values associated with the interrupts in a plurality of priority registers (PRIORITY REGISTERS),
- if no interrupt service routine (ISR) is running, carrying out the following operations:
- comparing the stored priority values of the pending interrupts identifying which of them (INTn) has the highest priority,
- serving the highest priority interrupt by generating an interrupt command (nIRQ) and an interrupt vector (IRQ VECTOR) identifying a respective interrupt service routine (ISR) to be run,
- canceling the served interrupt and its priority value from said registers,
- characterized in that the method comprises the steps of
- connecting a plurality of counters (PRIORITY COUNTERS) in cascade of said plurality of pending interrupts registers (INT PENDING REG);
- for each interrupt received, loading in a respective counter of said plurality the corresponding pre-established priority value associated to the received interrupt;
- incrementing at pre-established intervals the value loaded in said counters;
- comparing the updated priority values contained in said periodically incremented counters for identifying the interrupt (INTn) of the highest priority.
A control circuit for generating interrupt commands in a microprocessor system, comprising
- a pending interrupts register (INT PENDING REG), storing interrupts (INT0, . . . , INTm) received from peripherals,
- a plurality of priority registers (PRIORITY REGISTERS) storing priority values associated to respective interrupts (INT0, . . . , INTm), a priority comparing circuit (IRQ MASK AND PRIORITY LOGIC) coupled to said priority registers (PRIORITY REGISTERS) and to said pending interrupts register (INT PENDING REG), generating an interrupt request signal (IRQ REQ) and an internal signal (HIGHEST PRIORITY INT) representing the priority of the interrupt (INTn) of highest priority stored in said pending interrupts register (INT PENDING REG),
- a logic processing circuit (IRQ SM, IRQ VECTOR REG, IRQ VECTOR) of said interrupt request signal (IRQ REQ) and of said internal signal (HIGHEST PRIORITY INT) for sending to a system microprocessor an interrupt command (nIRQ) and an interrupt vector (IRQ VECTOR) identifying a certain interrupt service routine (ISR) to be executed,
- characterized by comprising further
- a plurality of counters (PRIORITY COUNTERS) coupled in cascade to said plurality of priority registers (PRIORITY REGISTERS) and means for initializing any of the counters with the priority value of a certain interrupt (INT0, . . . , INTm) to be served and for periodically incrementing the value by a respective increment signal (PRIORITY TRIGGERS) input to the register;
- said priority comparing circuit (IRQ MASK AND PRIORITY LOGIC) reading from said counters (PRIORITY COUNTERS) the priority associated to each interrupt (INT0, . . . , INTm) stored in said pending interrupts register (INT PENDING REG).
Dependencies are inferred from the claim text.