Graphics display system with unified memory architecture
AssigneeBroadcom Corporation
InventorsAlexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, James T. Patterson, Greg A. Kranawetter
Life of this patent
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Abstract
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
Claims3
A method for arbitrating access by a scheduling apparatus that provides an interface between a memory and at least two devices, the scheduling apparatus including a memory request arbiter configured to control access to the memory, wherein the memory request arbiter arbitrates access to the memory for different devices having different priorities, at least two counters coupled to the memory request arbiter, wherein each counter is associated with at least a first device of the at least two devices, and wherein at least one of the at least two counters is configured to produce various time-periods, wherein during such time-periods the arbiter prevents the first device from accessing the memory, wherein the scheduling apparatus provides scheduling of tasks, at least one of the tasks not inherently having a pre-determined periodic behavior, and wherein the scheduling apparatus is capable of arbitrating access to at least one device that is sensitive to latency, the method comprising:
- producing at least one time signal, the at least one time-signal defining a time-period;
- and
- preventing the first device from accessing the memory during the time-period.
A method for arbitrating access by a scheduling apparatus that provides an interface between a memory and at least two devices, the scheduling apparatus including a memory request arbiter configured to control access to the memory, wherein the memory request arbiter arbitrates access to the memory for different devices having different priorities, at least two counters coupled to the memory request arbiter, wherein each counter is associated with at least a first device of the at least two devices, and wherein at least one of the at least two counters is configured to produce various time-periods, wherein during such time-periods the arbiter prevents higher priority devices from accessing the memory, wherein the scheduling apparatus provides scheduling of tasks, at least one of the tasks not inherently having a pre-determined periodic behavior, and wherein the scheduling apparatus is capable of arbitrating access to at least one device that is sensitive to latency, the method comprising:
- producing at least one time signal, the at least one time-signal defining a time-period;
- and
- preventing higher priority devices from accessing the memory during the time-period.
A method for arbitrating access by a scheduling apparatus that provides an interface between a memory and at least two devices, the scheduling apparatus including a memory request arbiter configured to control access to the memory, wherein the memory request arbiter arbitrates access to the memory for different devices having different priorities, at least two counters coupled to the memory request arbiter, wherein each counter is associated with at least a first device of the at least two devices, and wherein at least one of the at least two counters is configured to produce various time-periods, wherein during such time-periods the associated device will not request high priority access from the memory, wherein the scheduling apparatus provides scheduling of tasks, at least one of the tasks not inherently having a pre-determined periodic behavior, and wherein the scheduling apparatus is capable of arbitrating access to at least one device that is sensitive to latency, the method comprising:
- producing at least one time signal, the at least one time-signal defining a time-period;
- and
- not allowing, during the time-period, high priority access to the memory by devices associated with the time-period.
Dependencies are inferred from the claim text.